Described is an apparatus which comprises: a current source to generate a current having AC and DC components; a current-to-voltage converter to convert the current or a copy of the current to a voltage proportional to a resistance, the voltage having AC and DC components that correspond to the AC and DC components of the current; a first sample-and-hold circuit to sample and filter the AC component from the voltage and to provide an output voltage with the DC component; a second sample-and-hold circuit to sample the output voltage; a voltage-to-current converter to convert the sampled output voltage to a corresponding current; and an amplifier to receive the output voltage.

Described is an apparatus which comprises: a current source to generate a current having AC and DC components; a current-to-voltage converter to convert the current or a copy of the current to a voltage proportional to a resistance, the voltage having AC and DC components that correspond to the AC and DC components of the current; a first sample-and-hold circuit to sample and filter the AC component from the voltage and to provide an output voltage with the DC component; a second sample-and-hold circuit to sample the output voltage; a voltage-to-current converter to convert the sampled output voltage to a corresponding current; and an amplifier to receive the output voltage.

A voltage divider circuit regarding a battery voltage and an associated electronic device equipped with the voltage divider circuit are provided. The voltage divider circuit may include a first level shifter circuit, a second level shifter circuit and a controlled voltage divider. The first level shifter circuit selectively performs a first level shifting operation on an original enable signal according to respective voltage levels of multiple control signals to generate a first enable signal. The second level shifter circuit selectively performs a second level shifting operation on the first enable signal according to a voltage level of the first enable signal to generate a second enable signal. The controlled voltage divider selectively performs a voltage dividing operation on the battery voltage according to a voltage level of the second enable signal to generate a divided voltage of the battery voltage to be an output of the voltage divider circuit.

At least one method, apparatus and system disclosed involves performing a dynamic voltage compensation in an integrated circuit. A first voltage on a first portion of an integrated circuit is received. A second voltage on a second portion of the integrated circuit is monitored. A determination is made as to whether the second voltage fell below the first voltage by a predetermined margin. A feedback adjustment of the of the second voltage is performed in response to a determination that the second voltage fell below the first voltage by the predetermined margin; the feedback adjustment comprises performing a step up of the second voltage.

At least one method, apparatus and system disclosed involves performing a dynamic voltage compensation in an integrated circuit. A first voltage on a first portion of an integrated circuit is received. A second voltage on a second portion of the integrated circuit is monitored. A determination is made as to whether the second voltage fell below the first voltage by a predetermined margin. A feedback adjustment of the of the second voltage is performed in response to a determination that the second voltage fell below the first voltage by the predetermined margin; the feedback adjustment comprises performing a step up of the second voltage.

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

A comparison circuit includes a comparator having a first input terminal receiving a first input voltage through a first capacitor, and a second input terminal receiving a second input voltage through a second capacitor, and an output terminal. A first switch has one end connected to the first input terminal and is turned on in a sample phase to set a voltage of the first input terminal as a voltage of the output terminal. A second switch has one end connected to the second input terminal and is turned on in the sample phase to set a voltage of the second input terminal as a reference voltage. A third switch is turned on in a comparison phase to equalize voltages of the other end of the first switch and the other end of the second switch.

A comparison circuit includes a comparator having a first input terminal receiving a first input voltage through a first capacitor, and a second input terminal receiving a second input voltage through a second capacitor, and an output terminal. A first switch has one end connected to the first input terminal and is turned on in a sample phase to set a voltage of the first input terminal as a voltage of the output terminal. A second switch has one end connected to the second input terminal and is turned on in the sample phase to set a voltage of the second input terminal as a reference voltage. A third switch is turned on in a comparison phase to equalize voltages of the other end of the first switch and the other end of the second switch.

A modulator spreads the spectrum of a generated clock to reduce Electro-Magnetic Interference (EMI). A capacitor is charged by a variable current to generate a ramp voltage that is compared to a reference to end a clock cycle and discharge the capacitor. An up-down counter drives a Digital-to-Analog Converter (DAC) that controls the variable charging current to provide triangle modulation. A smaller offset current is added or subtracted for cubic modulation when the up-down counter reaches its minimum count. A frequency divider that clocks the up-down counter also clocks a Linear-Feedback Shift-Register (LFSR) to that controls pseudo-random current sources that further modulate variable current and frequency. The LFSR is clocked with the up-down counter to modulate each frequency step, or only at the minimum count to randomly modulate at the minimum frequency. Binary-weighted bits from the up-down counter to the DAC are swapped to modulate the frequency step size.