A driver circuit for low voltage differential signaling, LVDS, includes a phase alignment circuit including an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and an output driver circuit coupled to the phase alignment circuit, the output driver circuit including a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal. Therein the phase alignment circuit is configured to provide the inverted internal signal with its phase being aligned to a phase of the internal signal.

Provided is a method for managing radio frequency (RF) and ultrasonic signals output by a generator that includes a surgical instrument comprising an RF energy output and an ultrasonic energy output and a circuit configured to receive a combined RF and ultrasonic signal from the generator. The method includes receiving a combined radio frequency (RF) and ultrasonic signal from a generator, generating a RF filtered signal by filtering RF frequency content from the combined signal; filtering ultrasonic frequency content from the combined signal; generating an ultrasonic filtered signal; providing the RF filtered signal to the RF energy output; and providing the ultrasonic filtered signal to the ultrasonic energy output.

Provided is a method for managing radio frequency (RF) and ultrasonic signals output by a generator that includes a surgical instrument comprising an RF energy output and an ultrasonic energy output and a circuit configured to receive a combined RF and ultrasonic signal from the generator. The method includes receiving a combined radio frequency (RF) and ultrasonic signal from a generator, generating a RF filtered signal by filtering RF frequency content from the combined signal; filtering ultrasonic frequency content from the combined signal; generating an ultrasonic filtered signal; providing the RF filtered signal to the RF energy output; and providing the ultrasonic filtered signal to the ultrasonic energy output.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

A signal processing circuit includes a signal path for outputting a first signal included in an input signal from a first output terminal to another signal processor; branch paths one of which extends from a top position located at a position on the signal path and the others which extend from associated branch positions that divide the signal path starting from the top position to the first output terminal into segments in each of which a first amount of delay obtained by equally dividing an amount of delay caused by the signal path and that is added to the first signal; a switch connected to each of the branch paths and switches whether to allow a second signal other than the first signal included in the input signal to pass through the connected branch paths; a variable gain amplifier connected to each of the switches and amplifies the second signal.

A signal processing circuit includes a signal path for outputting a first signal included in an input signal from a first output terminal to another signal processor; branch paths one of which extends from a top position located at a position on the signal path and the others which extend from associated branch positions that divide the signal path starting from the top position to the first output terminal into segments in each of which a first amount of delay obtained by equally dividing an amount of delay caused by the signal path and that is added to the first signal; a switch connected to each of the branch paths and switches whether to allow a second signal other than the first signal included in the input signal to pass through the connected branch paths; a variable gain amplifier connected to each of the switches and amplifies the second signal.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.