An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

A system for enhancing digital signal event counting is provided. The system includes a pulse filter coupled between a plurality of comparators and a plurality of counters. The pulse filter is configured to generate a refined signal associated with a rising edge and a falling edge of each comparator output corresponding to a threshold level. The pulse filter identifies the timing characterization of at least two refined signals respectively corresponding to a lower threshold level and a next higher threshold level and generates a trigger signal corresponding to an event counting based on the timing characterization associated with both the rising edge and the falling edge. Corresponding counters increment a count at the lower threshold level or both the lower threshold level and the next higher threshold level for each event counting based on the trigger signal.

A system for enhancing digital signal event counting is provided. The system includes a pulse filter coupled between a plurality of comparators and a plurality of counters. The pulse filter is configured to generate a refined signal associated with a rising edge and a falling edge of each comparator output corresponding to a threshold level. The pulse filter identifies the timing characterization of at least two refined signals respectively corresponding to a lower threshold level and a next higher threshold level and generates a trigger signal corresponding to an event counting based on the timing characterization associated with both the rising edge and the falling edge. Corresponding counters increment a count at the lower threshold level or both the lower threshold level and the next higher threshold level for each event counting based on the trigger signal.

Disclosed is an apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with non-reciprocal frequency conversion for electromagnetic isolation.

Disclosed is an apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with non-reciprocal frequency conversion for electromagnetic isolation.

Provided are a malicious attack protection circuit, a system-on-chip including the same, and an operating method thereof. The malicious attack protection circuit includes a reference interrupt generator to output a reference interrupt signal every reference interrupt period, a variable clock manager for outputting an operating clock signal to a logic circuit outside the malicious attack protection circuit and a variable clock signal having a variable period, a variable interrupt generator to output an interrupt signal every variable interrupt period based on the variable clock signal, a comparison circuit to compare the reference interrupt signal with the interrupt signal and output a comparison result signal, and a controller that interrupts the output of the operating clock signal input to the logic circuit, according to the comparison result signal.

Various aspects of the present disclosure generally relate to memory devices. In some aspects, a device may generate a clock signal for a memory interface. The device may apply a clock leveling to one or more initial clock pulses associated with the clock signal. The device may stop the clock leveling for one or more remaining clock pulses associated with the clock signal. Numerous other aspects are described.

Various aspects of the present disclosure generally relate to memory devices. In some aspects, a device may generate a clock signal for a memory interface. The device may apply a clock leveling to one or more initial clock pulses associated with the clock signal. The device may stop the clock leveling for one or more remaining clock pulses associated with the clock signal. Numerous other aspects are described.