An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

An apparatus includes a regulator, a modulation circuit, a first delay generator, and a second delay generator. The regulator generates a regulator control output signal to control a current of a power converter to regulate an output voltage of the power converter, the modulation circuit modulates a switching frequency of the power converter, the first delay generator controls a first delay time to turn on a switch of the power converter in a switching cycle, based on a change in the switching frequency of the power converter, and the second delay generator controls a second delay time to turn the switch of the power converter off in the switching cycle, based on the first delay time and a duty cycle of the power converter.

An apparatus includes a regulator, a modulation circuit, a first delay generator, and a second delay generator. The regulator generates a regulator control output signal to control a current of a power converter to regulate an output voltage of the power converter, the modulation circuit modulates a switching frequency of the power converter, the first delay generator controls a first delay time to turn on a switch of the power converter in a switching cycle, based on a change in the switching frequency of the power converter, and the second delay generator controls a second delay time to turn the switch of the power converter off in the switching cycle, based on the first delay time and a duty cycle of the power converter.

A voltage pulse generator comprising: circuitry controllable to generate a voltage pulse at an output of the circuitry; and an interruptor that monitors voltage at the output during a transition edge of the voltage pulse and interrupts a voltage change associated with the transition edge if the monitored voltage differs from a predetermined reference voltage by a predetermined amount.

A voltage pulse generator comprising: circuitry controllable to generate a voltage pulse at an output of the circuitry; and an interruptor that monitors voltage at the output during a transition edge of the voltage pulse and interrupts a voltage change associated with the transition edge if the monitored voltage differs from a predetermined reference voltage by a predetermined amount.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

A signal transmission circuit is connected to a positive electrode of a direct current power supply line, the signal transmission circuit includes a modulation circuit and/or a demodulation circuit, the modulation circuit includes a modulation chip, the modulation chip is used to receive an input signal, generate a modulation signal according to the input signal, and output the modulation signal through the positive electrode of the power supply line; the demodulation circuit includes a direct current isolation unit and a demodulation unit, the direct current isolation unit is connected to the demodulation unit and the positive electrode of the power supply line respectively, the direct current isolation unit is used to isolate a direct current signal of the positive electrode of the power supply line, and output the modulation signal; the demodulation unit is used to demodulate and output the modulation signal.

A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.

In a control apparatus for a power converter, a current obtainer obtains a current flowing through an inductor as an inductor current, and an alternating-current voltage obtainer obtains an alternating-current voltage. A drive signal outputting unit generates, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command. The drive signal outputting unit performs peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command. A delay unit delays, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage. The drive signal defines the off-switching timing of the switch.