In a control apparatus for a power converter, a current obtainer obtains a current flowing through an inductor as an inductor current, and an alternating-current voltage obtainer obtains an alternating-current voltage. A drive signal outputting unit generates, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command. The drive signal outputting unit performs peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command. A delay unit delays, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage. The drive signal defines the off-switching timing of the switch.

A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.

A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.

Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

A delay circuit is disclosed. The delay circuit is coupled to a relay switch that is contained in a power conversion device. When an electronic device having the power conversion device is operated in a sleep mode, the delay circuit applies a time delaying process to a power signal that is transmitted to the relay switch, such that a rising time of each of switch-on pulses contained by the power signal is delayed for a specific time. The specific time is set to be longer than a pulse width of each of power-on pulses contained by a power switching signal of the power conversion device. As such, when the electronic device is operated in the sleep mode, switching actions of the relay switch is properly controlled, thereby making the power conversion device not produce noise. Moreover, the service life of the relay unit is also extended.

A delay circuit is disclosed. The delay circuit is coupled to a relay switch that is contained in a power conversion device. When an electronic device having the power conversion device is operated in a sleep mode, the delay circuit applies a time delaying process to a power signal that is transmitted to the relay switch, such that a rising time of each of switch-on pulses contained by the power signal is delayed for a specific time. The specific time is set to be longer than a pulse width of each of power-on pulses contained by a power switching signal of the power conversion device. As such, when the electronic device is operated in the sleep mode, switching actions of the relay switch is properly controlled, thereby making the power conversion device not produce noise. Moreover, the service life of the relay unit is also extended.

A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.