Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.

Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.

A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.