Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present in the clocks output by these DLL elements. A plurality of DLL elements are interconnected/coupled such that a root input clock is successively relayed down a series of DLL elements. The output clocks from each of these DLL elements are interconnected/coupled to phase-corresponding output clocks from DLL elements in the series. This reduces the amount of phase error on these output clocks when compared to DLL elements that do not have outputs coupled to each other.

Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.

A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.

A tunable delay circuit includes a first multiplexer, a delay chain, and a second multiplexer. The first multiplexer selects an input signal or a feedback signal as a first output signal according to an enable signal. The delay chain delays the first output signal for different time periods so as to generate a plurality of delay signals. One of the delay signals is used as the feedback signal. The second multiplexer selects one of the delay signals as a second output signal according to a pass signal.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.