A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

A clock signal generation circuit for a switched capacitor circuit with a chopping function unit includes: first and second synchronous clock circuits that generate first and second synchronous clock signals, respectively; an edge signal generation circuit that generates one or more rise and fall edge signals by delaying the first synchronous clock signal; a first clock generator that generate a first clock signal group for driving the switched capacitor circuit; and a second clock generator that generates a second clock signal group for driving the chopping function unit. Frequencies of the first and second clock signal groups are respectively defined by the first and second synchronous clock circuits. Rise and fall edges of the first and second clock signal groups are defined by the edge signal generation circuit.

In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and being arranged as a standing wave resonator. At least one of the at least one resonator rib has a thickness that varies along a length of the respective one of the at least one resonator rib. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line can be conductively coupled to an associated circuit and being inductively coupled to the at least one resonator rib to inductively generate a clock current corresponding to the clock signal to provide functions for the associated circuit.

The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.

A detector circuit includes a calculator circuit and a comparator circuit. The calculator circuit is configured to generate a plurality of first calculation values according to a plurality of first calculation symbols of a Pseudo-Noise Sequence and a plurality of second calculation symbols of a received signal, and generate a second calculation value according to the first calculation values. If a sign of a symbol of the Pseudo-Noise Sequence is the same to a sign of an adjacent symbol, the symbol is one of the first calculation symbols, and the second calculation symbols are corresponding to the first calculation symbols respectively. The comparator circuit is configured to generate a comparison result according to the second calculation value and a threshold value. The comparison result is configured for determining whether the detector circuit correctly receives the Pseudo-Noise Sequence.

A detector circuit incudes a calculator circuit and a comparator circuit. The calculator circuit is configured to generate a plurality of first calculation values according to a plurality of first calculation symbols of a Pseudo-Noise Sequence and a plurality of second calculation symbols of a received signal, and generate a second calculation value according to the first calculation values. If a sign of a symbol of the Pseudo-Noise Sequence is the same to a sign of an adjacent symbol, the symbol is one of the first calculation symbols, and the second calculation symbols are corresponding to the first calculation symbols respectively. The comparator circuit is configured to generate a comparison result according to the second calculation value and a threshold value. The comparison result is configured for determining whether the detector circuit correctly receives the Pseudo-Noise Sequence.

A fifty percent duty cycle detector includes a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine configured to receive the digital word and output the logical control signal and a ternary decision.

A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.