A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.

A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. A gate driver is operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device. The gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device.

In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

Techniques are described herein for phase modulation and interpolation that support high phase modulation resolution with high linearity. Embodiments receive a digital signal that uses a sequence of K-bit digital codes to encode a sequence of instantaneous phases for phase-modulating a local oscillator signal. A fractional divider divides a reference clock into N divided clock signals at equally spaced phase intervals and selects a pair of such signals based on first designated bits of the digital code. A fractional divider-calibrated delay line generates M delayed clock signals at equally spaced phase intervals between the selected pair of divided clock signals, and selects a pair of the delayed clock signals based on second designated bits of the digital code. A digital controlled edge interpolator generates a delayed local oscillator output signal by interpolating between the selected pair of delayed clock signals based on third designated bits of the digital code.

A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.