Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals.

An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals.

A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

The Direct Synthesis of a Receiver Clock (DSRC) contributes a method, system and apparatus for reliable and inexpensive synthesis of inherently stable local clock synchronized to a referencing signal received from an external source. Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver. Such DSRC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI or Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.

A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.