Provided are embodiments for a system including a zero-cross circuit. The system includes a first channel and a second channel Each channel includes a generator, a generator relay, and a bus tie relay. In addition, the system includes a zero-cross circuit, wherein the zero-cross circuit synchronizes the operation of the first and second channel, and at least one controller configured to control the operation of the first channel and the second channel based on an input from the zero-cross circuit. Also provided is a method for operating the zero-cross circuit with low phase delay. The method includes receiving an inverting input, receiving a non-inverting input, and comparing the inverting input and the non-inverting input. The method also includes receiving feedback from an output of the comparator; and outputting a waveform based on the comparison of the inverting input and the non-inverting input and the feedback.

Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

A voltage detector includes a voltage division circuit which outputs a divided voltage based on an input voltage, a comparison circuit which compares the divided voltage and a reference voltage to output a detection signal and a release signal, and a voltage limiting circuit which limits the divided voltage to a preset voltage.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n1, and the third number is 1, the total number of resistors is 2n.

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n1, and the third number is 1, the total number of resistors is 2n.

A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit comprises: a latch and a signal output module, wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module. The power glitch signal detection circuit could detect a power glitch on the power supply voltage or the ground voltage, and the power glitch signal detection circuit has the advantages of low power consumption, small area, high speed, high sensitivity and strong portability.

A circuit assembly for monitoring a sinusoidal alternating voltage signal having a comparing element receiving at an input the signal with period T and generating a first output signal at an output based upon the signal exceeding a threshold; a zero crossing detector receives at its input the signal and generates a output signal at its output; a timing element connected to zero crossing detector generates a clock signal dependent on the second output signal; and a flip-flop. The comparing element output is connected to a state-controlled input of the flip-flop and the timing element output is connected to an edge-controlled input of the flip-flop. The flip-flop generates a state signal at its output. The timing element specifies a state change of the clock signal at an instant that differs from the instant at T/4 after a zero crossing of the signal.

A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

Provided is a defect judging unit for a measuring probe including: a stylus; four detection elements; and a signal processing part. The defect judging unit includes a defect judging part configured to compare four judged signals corresponding to the generated signals with predetermined thresholds when the object to be measured and the contact part are out of contact with each other and judge that a defect exists if any of the judged signals is greater than the predetermined threshold, and a judged result output part configured to output a judged result of the defect judging part. According to this configuration, the defect judging unit of the measuring probe and the defect judging method thereof capable of ensuring measurement reliability with a simple configuration are provided.