An input circuit for detecting low voltage analog signals in an electrically noisy environment receives the analog input signal at an input terminal. The analog input signal is compared to a variable reference signal at a comparator circuit. An active hysteresis circuit provides feedback to the comparator. In a first operating mode, the active hysteresis circuit may be disabled or be configured to output a constant voltage. In a second operating mode, the active hysteresis circuit may be enabled or configured to output a varying level of voltage. The output of the feedback circuit is summed with the variable reference signal and supplied as the input signal to the comparator, such that signal against which the analog input signal is compared is a general constant value in the first operating mode and varies with respect to time in the second operating mode.

A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.

Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.

A sequence circuit (1) includes a detector (2) that detects an occurrence of an event based on an input signal, an acceptor (4) that accepts the event whose occurrence has been detected by the detector, an inhibitor (4) that inhibits the acceptor from accepting another event for a first period using the acceptance of one event by the acceptor as a trigger, a clock pulse generator (3) that generates one or more clock pulses during a period after a second period shorter than the first period elapses from the start of the first period until the first period ends, a determiner (5) that determines a next state based on a current slate and the event accepted by the acceptor, and a latch (6) that latches the next state using the clock pulse. An output of the latch is the current state.

A sequence circuit (1) includes a detector (2) that detects an occurrence of an event based on an input signal, an acceptor (4) that accepts the event whose occurrence has been detected by the detector, an inhibitor (4) that inhibits the acceptor from accepting another event for a first period using the acceptance of one event by the acceptor as a trigger, a clock pulse generator (3) that generates one or more clock pulses during a period after a second period shorter than the first period elapses from the start of the first period until the first period ends, a determiner (5) that determines a next state based on a current slate and the event accepted by the acceptor, and a latch (6) that latches the next state using the clock pulse. An output of the latch is the current state.

Systems and methods are disclosed for a two lead electronic switch adapted to replace a mechanical switch. In one embodiment, a device is provided that includes a sensor and an electronic circuit having a voltage limiting circuit. The electronic circuit is configured to deactivate/activate the voltage limiting circuit to operate the electronic circuit in a first/second state in response to determining that an output of the sensor is less/more than a threshold voltage. The circuit includes first and second terminals configured to receive a switch voltage used to provide power for the device. The device sets the switch voltage to a first voltage level operative to power the electronic circuit and the sensor while the electronic circuit is operating in the first state and to a second voltage level operative to power the electronic circuit and the sensor while the electronic circuit is operating in the second state.

Systems and methods are disclosed for a two lead electronic switch adapted to replace a mechanical switch. In one embodiment, a device is provided that includes a sensor and an electronic circuit having a voltage limiting circuit. The electronic circuit is configured to deactivate/activate the voltage limiting circuit to operate the electronic circuit in a first/second state in response to determining that an output of the sensor is less/more than a threshold voltage. The circuit includes first and second terminals configured to receive a switch voltage used to provide power for the device. The device sets the switch voltage to a first voltage level operative to power the electronic circuit and the sensor while the electronic circuit is operating in the first state and to a second voltage level operative to power the electronic circuit and the sensor while the electronic circuit is operating in the second state.

A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.

A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.

A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.