An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.

Systems and methods for identifying a single failure in a heater array and compensating for the failure are described. The methods include identifying two X buses and two Y buses of the heater array having a location of the failure. A confirmation of the single failure within the heater array is performed after identifying the two X and two Y buses. Once the single failure is confirmed, the location of the failure is identified. The methods include compensating for the single failure by adjusting a duty cycle of a heater at the location of the failure, adjusting additional duty cycles of heaters along the same X bus as the failed heater and the same Y bus as the failed heater, and maintaining remaining duty cycles of power provided to remaining heaters of the heater array.

A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.

Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

An electronic device includes a driver circuit embodied on an IC chip. The driver circuit includes a threshold voltage selection circuit that is coupled to receive a horn comparator threshold setting and to use the horn comparator threshold setting to provide a horn comparator threshold voltage. The driver circuit also includes a comparator that has a non-inverting input coupled to a first pin and an inverting input coupled to receive the horn comparator threshold voltage.

The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.

A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

A controller device for controlling an effective value of an electric load current at a time-variant load is provided. The controller device provides at the time-variant load a voltage pulse sequence having a duty cycle in at least one pulse phase of the voltage pulse sequence. A sample value of the electric load current is acquired at the time-variant load, to determine an actual effective value of the electric load current using a dependency stored in the controller device. The actual effective value is assigned to the sample value of the electric load current. A difference value between the actual effective value of the electric load current and a setpoint effective value of the electric load current is determined, and adapted duty cycle of the voltage pulse sequence is determined from the difference value, and provides at the time-variant load an adapted voltage pulse sequence having the adapted duty cycle.

A controller device for controlling an effective value of an electric load current at a time-variant load is provided. The controller device provides at the time-variant load a voltage pulse sequence having a duty cycle in at least one pulse phase of the voltage pulse sequence. A sample value of the electric load current is acquired at the time-variant load, to determine an actual effective value of the electric load current using a dependency stored in the controller device. The actual effective value is assigned to the sample value of the electric load current. A difference value between the actual effective value of the electric load current and a setpoint effective value of the electric load current is determined, and adapted duty cycle of the voltage pulse sequence is determined from the difference value, and provides at the time-variant load an adapted voltage pulse sequence having the adapted duty cycle.

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.