An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

A monitor for an electrical control system has a pulse detection circuit configured to detect a voltage waveform output to an electrified element. The monitor also has a monitor processor. The monitor processor receives the voltage waveform from the pulse detection circuit, measures one or more parameters of the voltage waveform, receives additional information associated with the voltage waveform, compares the one or more parameters to the additional information, and performs an analysis process based on the comparison of the voltage waveform and the additional information. The monitor also has a communication interface configured to deliver a result of the analysis process to an interface component via one or more communication components connected to the monitor processor.

A monitor for an electrical control system has a pulse detection circuit configured to detect a voltage waveform output to an electrified element. The monitor also has a monitor processor. The monitor processor receives the voltage waveform from the pulse detection circuit, measures one or more parameters of the voltage waveform, receives additional information associated with the voltage waveform, compares the one or more parameters to the additional information, and performs an analysis process based on the comparison of the voltage waveform and the additional information. The monitor also has a communication interface configured to deliver a result of the analysis process to an interface component via one or more communication components connected to the monitor processor.

A windowed watchdog circuit system can include a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold. The windowed watchdog circuit system can include a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorted than the fast threshold. The windowed watchdog circuit system can be configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

A signal processing apparatus includes a processor, a memory storing a program, and an integration circuit that performs filter processing on an input signal to output a processed signal. The processor samples an output signal output from the integration circuit in a sampling period Ts and stores a sampled value of the output signal in accordance with the program, and detects a duty of the input signal based on a difference between a value of the output signal at a time t.sub.0 representing a present time point and a sampled value of the output signal obtained at a time t.sub.0−n representing an earlier time than the time t.sub.0 by an n sampling period when n is a positive integer, the value of the output signal, a value of the integer n, the sampling period Ts, and a time constant of a filter of the integration circuit.

Method for activating a feature of a chip having an interface comprising at least two power pins. The method comprises the following steps: the chip measures a series of voltage values between said power pins, the chip detects a series of sync signals different from clock signals, said sync signals being interleaved with said voltage values, the chip identifies a data sequence from said series of voltage values, and the chip activates the feature only if the data sequence matches a predefined pattern.

Implementations of conductive energy weapons (CEWs) may include a shock generating circuit configured to couple to a power source, two electrodes operatively coupled to the shock generating circuit, and a safety circuit operatively coupled to the shock generating circuit. The shock generating circuit may be configured to generate a first pulse train and deliver the first pulse train to a target, and may be configured to generate at least a second pulse train and deliver the at least second pulse train to a target. The safety circuit may be configured to prevent the CEW from applying pulse trains to the target after a predetermined number of pulse trains. The first pulse train may include two or more pulses having waveforms substantially identical with each other, each of the waveforms of the two or more pulses having both a positive voltage segment and a negative voltage segment.

Implementations of conductive energy weapons (CEWs) may include a shock generating circuit configured to couple to a power source, two electrodes operatively coupled to the shock generating circuit, and a safety circuit operatively coupled to the shock generating circuit. The shock generating circuit may be configured to generate a first pulse train and deliver the first pulse train to a target, and may be configured to generate at least a second pulse train and deliver the at least second pulse train to a target. The safety circuit may be configured to prevent the CEW from applying pulse trains to the target after a predetermined number of pulse trains. The first pulse train may include two or more pulses having waveforms substantially identical with each other, each of the waveforms of the two or more pulses having both a positive voltage segment and a negative voltage segment.