A method corrects at least one transmission parameter for data transmission between a sensor unit and a control unit. A sensor timing signal is generated by a sensor oscillator with a predetermined period. The at least one transmission parameter is determined on the basis of the sensor timing signal. A reference timing signal is generated by a reference oscillator with a predefined reference period. The sensor timing signal is compared with the reference timing signal. A deviation of a current period of the sensor timing signal from a reference period is determined on the basis of the comparison. The at least one transmission parameter is corrected on the basis of the determined deviation.

A method corrects at least one transmission parameter for data transmission between a sensor unit and a control unit. A sensor timing signal is generated by a sensor oscillator with a predetermined period. The at least one transmission parameter is determined on the basis of the sensor timing signal. A reference timing signal is generated by a reference oscillator with a predefined reference period. The sensor timing signal is compared with the reference timing signal. A deviation of a current period of the sensor timing signal from a reference period is determined on the basis of the comparison. The at least one transmission parameter is corrected on the basis of the determined deviation.

The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.

Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.

Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n1, and the third number is 1, the total number of resistors is 2n.

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n1, and the third number is 1, the total number of resistors is 2n.

A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).