A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.

A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.

A method for preparing photoactive perovskite materials. The method comprises the steps of preparing a lead and tin halide precursor ink. Preparing a lead and tin halide precursor ink comprises the steps of introducing a lead halide and a tin halide into a vessel; introducing a first solvent to the vessel; and contacting the lead halide and the halide with the first solvent to dissolve the lead halide and the tin halide to form the lead and tin halide precursor ink; depositing the lead and tin halide precursor ink onto a substrate; drying the lead and tin halide precursor ink to form a thin film; annealing the thin film; and rinsing the thin film with a solvent comprising: a second solvent; a first salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide; and a second salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide.

A method for preparing photoactive perovskite materials. The method comprises the steps of preparing a lead and tin halide precursor ink. Preparing a lead and tin halide precursor ink comprises the steps of introducing a lead halide and a tin halide into a vessel; introducing a first solvent to the vessel; and contacting the lead halide and the halide with the first solvent to dissolve the lead halide and the tin halide to form the lead and tin halide precursor ink; depositing the lead and tin halide precursor ink onto a substrate; drying the lead and tin halide precursor ink to form a thin film; annealing the thin film; and rinsing the thin film with a solvent comprising: a second solvent; a first salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide; and a second salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide.

A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

A hot swap controller circuit includes a comparator and current control circuitry. The comparator is configured to compare voltage across a power transistor controlled by the hot swap controller circuit to a predetermined threshold voltage. The current control circuitry is coupled to the comparator. The current control circuitry is configured to limit current through the power transistor to no higher than a predetermined high current based on the voltage across the transistor being less than the predetermined threshold voltage. The current control circuitry is also configured to limit the current through the transistor to be no higher than a predetermined low current based on the voltage across the transistor being greater than the predetermined threshold voltage. The predetermined high current is greater than the predetermined low current.

A hot swap controller circuit includes a comparator and current control circuitry. The comparator is configured to compare voltage across a power transistor controlled by the hot swap controller circuit to a predetermined threshold voltage. The current control circuitry is coupled to the comparator. The current control circuitry is configured to limit current through the power transistor to no higher than a predetermined high current based on the voltage across the transistor being less than the predetermined threshold voltage. The current control circuitry is also configured to limit the current through the transistor to be no higher than a predetermined low current based on the voltage across the transistor being greater than the predetermined threshold voltage. The predetermined high current is greater than the predetermined low current.

System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.