In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.

A method for synchronizing acquisition of an analog signal value with a read signal for a state of an electrical contact of a motor vehicle. The method includes: controlling, at each start time of the first task, the power supply module so that the power supply module generates a read signal voltage pulse at the interface module input; at the same start time, triggering a counter for a predetermined duration shorter than the duration of the read signal voltage pulse; on the expiration of the counter duration, measuring the value of an analog signal generated by the interface module based on the state signal and of the read signal; and controlling, at the next start time of the second task, the power supply module so that the power supply module generates a zero voltage signal at the interface module input until the next start time of the first task.

A method for synchronizing acquisition of an analog signal value with a read signal for a state of an electrical contact of a motor vehicle. The method includes: controlling, at each start time of the first task, the power supply module so that the power supply module generates a read signal voltage pulse at the interface module input; at the same start time, triggering a counter for a predetermined duration shorter than the duration of the read signal voltage pulse; on the expiration of the counter duration, measuring the value of an analog signal generated by the interface module based on the state signal and of the read signal; and controlling, at the next start time of the second task, the power supply module so that the power supply module generates a zero voltage signal at the interface module input until the next start time of the first task.

An oscillation period detection circuit and method, and semiconductor memory are provided. The oscillation period detection circuit includes an oscillator module, a control module, and a counting module. The oscillator module includes a target oscillator, and is configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; the control module is configured to receive the enable signal and the oscillation clock signal, and perform valid time reforming processing according to the oscillation clock signal and the enable signal to determine a target time; the counting module is configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated according to the target time and the target period number.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.

A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

A device capable of processing a pilot control signal having at least two modes: continuous or alternating PWM, and of generating a binary detection signal, the state of which is an indication of the mode, the device having a voltage doubler and a comparator.

A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.