A detection device has a detecting port, a leakage port, an oscillation circuit and a detection circuit. The detecting port is used for pluggably coupled to an object. The leakage port is electrically coupled to a ground loop. The oscillation circuit is respectively coupled to the detecting port and the leakage port, and used for generating an oscillation signal. When the detecting port is coupled to the object, electrons on the object are transferred to the leakage port via the oscillation circuit. The detection circuit is used for determining whether the detecting port is coupled to the object based on the oscillation characteristic of the oscillation signal.

A detection device has a detecting port, a leakage port, an oscillation circuit and a detection circuit. The detecting port is used for pluggably coupled to an object. The leakage port is electrically coupled to a ground loop. The oscillation circuit is respectively coupled to the detecting port and the leakage port, and used for generating an oscillation signal. When the detecting port is coupled to the object, electrons on the object are transferred to the leakage port via the oscillation circuit. The detection circuit is used for determining whether the detecting port is coupled to the object based on the oscillation characteristic of the oscillation signal.

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

The present disclosure provides a method and a device for processing PWM data, so as to reduce the size of the PWM data. The method includes: dividing pulse widths in the PWM data into at least one pulse width group; determining a convergence pulse width for each of the at least one pulse width group, herein each of the at least one pulse width group converges around a same pulse width, respectively; replacing each of the at least one pulse width group with the corresponding convergence pulse width; and representing the PWM data by using the convergence pulse widths. Through the technical solution, the size of the PWM data may be reduced, transmission speed of the PWM data may be improved, and the space for storing the PWM data may be decreased.

The present disclosure provides a method and a device for processing PWM data, so as to reduce the size of the PWM data. The method includes: dividing pulse widths in the PWM data into at least one pulse width group; determining a convergence pulse width for each of the at least one pulse width group, herein each of the at least one pulse width group converges around a same pulse width, respectively; replacing each of the at least one pulse width group with the corresponding convergence pulse width; and representing the PWM data by using the convergence pulse widths. Through the technical solution, the size of the PWM data may be reduced, transmission speed of the PWM data may be improved, and the space for storing the PWM data may be decreased.

Disclosed is an electronic circuit with a first terminal for connecting an accessory thereto, and with a functionality for detecting the presence of an accessory connected to the first terminal.

Disclosed is an electronic circuit with a first terminal for connecting an accessory thereto, and with a functionality for detecting the presence of an accessory connected to the first terminal.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.