The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.

The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Disclosed are circuits and methods for a comparator with a floating capacitive supply. A capacitor is coupled between a comparator and a power supply. Two sets of electronic switches are configured in opposing operational states to shift the configuration of the circuit between a charging configuration and a decision configuration. In the charging configuration, the capacitor draws current from the power supply. In the decision configuration, the comparator pulls current from the capacitor to perform a decision. The configuration of the two sets of switches is alternated to toggle between the charging configuration and the decision configuration, allowing for the capacitor to be recharged between each decision performed by the comparator.

An example of an apparatus includes a bias circuit having first and second bias circuit outputs. The apparatus also includes a comparator having first and second comparator inputs. The apparatus also includes a first capacitor coupled between the second comparator input and the second bias circuit output. The apparatus also includes a first switch coupled between the second comparator input and the second bias circuit output. The apparatus also includes a second switch coupled between the first bias circuit output and an input terminal, a third switch coupled between the input terminal and the first comparator input, and a fourth switch coupled between the first bias circuit output and the first comparator input. The apparatus also includes a second capacitor coupled between the first comparator input and the second bias circuit output.

A driving apparatus includes a current output unit, a reference voltage output unit, a comparator, and a drive control unit. The current output unit is switchable to either a first ON resistance or a second ON resistance that is N times (N>1) the first ON resistance. The reference voltage output unit outputs a fist reference voltage during a large current time period, and outputs a second reference voltage that is M times (M>1) the first reference voltage during a small current time period. The drive control unit performs control to perform switching to the first ON resistance during the large current time period, and to perform switching to the second ON resistance during the small current time period.

A driving apparatus includes a current output unit, a reference voltage output unit, a comparator, and a drive control unit. The current output unit is switchable to either a first ON resistance or a second ON resistance that is N times (N>1) the first ON resistance. The reference voltage output unit outputs a fist reference voltage during a large current time period, and outputs a second reference voltage that is M times (M>1) the first reference voltage during a small current time period. The drive control unit performs control to perform switching to the first ON resistance during the large current time period, and to perform switching to the second ON resistance during the small current time period.

A transmit signal generator is provided. The transmit signal generator has an n−1 bit comparator having a first set of n−1 input lines and a second set of n−1 input lines and an output line, the n−1 bit comparator operable to compare signals of the first set of n−1 input lines and signals of the second set of n−1 input lines and provide the output of the n−1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n−1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.

Disclosed is an integrated circuit having a trim function for an embedded analog component or digital component. The integrated circuit includes a trim value generator configured to provide a varying trim value, a measurement target selected from a digital component and an analog component and configured to provide a measured value as a result of an internal operation corresponding to the trim value, a determination unit configured to determine the measured value based on a reference value received from the outside and to provide a trim control signal when the measured value corresponds to a preset target value, and a storage configured to store a current trim value as a measured result value in response to the trim control signal.