Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

The present disclosure provides for distortion cancelled by receiving a collided signal comprising first and second signals carrying respective first and second packets; digitizing the collided signal into a first digital signal and decoding the first packet therefrom; calculating a digital linear interference component of the first packet on the second from an estimated signal re-encoding the decoded first packet; synthesizing an analog linear interference component from the digital linear interference component; determining a digital nonlinear interference component of the first packet on the second from the first digital signal; amplifying the collided signal to produce a second amplified signal; removing the analog linear interference component from the second amplified signal to produce a partially de-interfered signal; removing the digital nonlinear interference component from the partially de-interfered signal to produce a de-interfered signal; and decoding the second packet from the de-interfered signal.

A timing estimation device according to the present invention includes a received signal memory that outputs a plurality of sample groups each of which is a first number of samples extracted at symbol rate intervals from an oversampled received signal containing a known sequence, with shifting their leading positions by one sample from each other, a reliability calculation unit that calculates a channel impulse response for each of the sample groups, based on the sample group, generates a replica of the received signal using the channel impulse response and the known sequence, and calculates a reliability value based on the sample group, the replica, and the channel impulse response, and a timing estimation unit that estimates a preceding wave arrival timing and a delayed wave arrival timing, based on the reliability value.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

The present disclosure provides for distortion cancelled by receiving a collided signal, the collided signal comprising a first signal carrying a first packet and a second signal carrying a second packet; amplifying and digitizing the collided signal into a first digital signal at a first gain and a second digital signal at a second gain that is greater than the first gain; determining a nonlinear interference component of the first packet on the second packet from the first digital signal; decoding the first packet from the first digital signal; re-encoding the first packet with a first estimated channel effect into an estimated signal; calculating a linear interference component of the first packet on the second packet from the estimated signal; removing the linear interference component and the nonlinear interference component from the second digital signal to produce a de-interfered signal; and decoding the second packet from the de-interfered signal.

A transmitter circuit is provided in the present disclosure. The transmitter circuit includes a first capacitance, a first current pump circuit for charging or discharging the first capacitance to output a first voltage, a second capacitance, and a second current pump circuit for charging or discharging the second capacitance to output a second voltage. A charging rate at which the first current pump circuit charges the first capacitance or a discharging rate at which the first current pump circuit discharges the first capacitance determines a rising slew rate or a falling slew rate of the first voltage. A charging rate at which the second current pump circuit charges the second capacitance or a discharging rate at which the second current pump circuit discharges the second capacitance determines a rising slew rate or a falling slew rate of the second voltage.

A transmitter circuit is provided in the present disclosure. The transmitter circuit includes a first capacitance, a first current pump circuit for charging or discharging the first capacitance to output a first voltage, a second capacitance, and a second current pump circuit for charging or discharging the second capacitance to output a second voltage. A charging rate at which the first current pump circuit charges the first capacitance or a discharging rate at which the first current pump circuit discharges the first capacitance determines a rising slew rate or a falling slew rate of the first voltage. A charging rate at which the second current pump circuit charges the second capacitance or a discharging rate at which the second current pump circuit discharges the second capacitance determines a rising slew rate or a falling slew rate of the second voltage.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.