System and method for beamspace nonlinear equalization in a plurality of parallel channels includes: receiving M parallel signals for transmission by N channels, respectively, wherein M is an integer greater than or equal to 1 and N is an integer greater than 1; performing a linear transfer function on each of the M parallel signal by a finite impulse response (FIR) filter; adding FIR filter tap outputs to each M parallel signals, respectively; phase shifting an output of a respective FIR filter per each of the M parallel signals to generate M intermediate channelized output signals per each of the N channels; summing, by a single summer, the M intermediate channelized output signals across the N channels to produce M channelized polyphase output signals; serializing the M channelized polyphase output signals to generate serialized M polyphase output signals; and equalizing the serialized M polyphase output signals to produce a linearized signal in beamspace.

A transmitter circuit is provided in the present disclosure. The transmitter circuit includes a first capacitance, a first current pump circuit for charging or discharging the first capacitance to output a first voltage, a second capacitance, and a second current pump circuit for charging or discharging the second capacitance to output a second voltage. A charging rate at which the first current pump circuit charges the first capacitance or a discharging rate at which the first current pump circuit discharges the first capacitance determines a rising slew rate or a falling slew rate of the first voltage. A charging rate at which the second current pump circuit charges the second capacitance or a discharging rate at which the second current pump circuit discharges the second capacitance determines a rising slew rate or a falling slew rate of the second voltage.

A device for generating a ramp signal with a changing slope is disclosed. The device may comprise a processor configured to generate a variable signal. The device may also comprise a phase-locked loop (PLL) circuit configured to receive the variable signal and a reference clock signal, generate a changing ramp clock signal based on the variable signal and the reference clock signal, and output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.

A device for generating a ramp signal with a changing slope is disclosed. The device may comprise a processor configured to generate a variable signal. The device may also comprise a phase-locked loop (PLL) circuit configured to receive the variable signal and a reference clock signal, generate a changing ramp clock signal based on the variable signal and the reference clock signal, and output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.

A receiver includes circuitry configured to determine one or more first local oscillator (LO) harmonics that correspond to one or more first spectrum segments of a down-converted received signal based on characteristics of the received signal. The one or more first LO harmonics of the received signal are amplified by applying one or more first transconductance coefficients to one or more first harmonic selective transinductance amplifiers (TIAs) corresponding to the one or more first spectrum segments. Digitized outputs of the plurality of harmonic selective TIAs are calibrated based on an amount of signal leakage between the plurality of spectrum segments of the down-converted received signal.

A down-conversion circuit for a receiver circuit is disclosed, the down-conversion circuit comprises a first passive switching mixer arranged to down-convert a received radio frequency, RF, signal with a first local oscillator, LO, signal (LO1) having a first duty cycle for generating a first down-converted signal at an output port of the first passive switching mixer. The down-conversion circuit further comprises a second passive switching mixer arranged to down-convert the received RF signal with a second LO signal (LO2) having the same LO frequency as the first LO signal (LO1) and a second duty cycle, different from the first duty cycle, for generating a second down-converted signal at an output port of the second passive switching mixer. In addition, the down-conversion circuit comprises a passive output combiner network operatively connected to the output ports of the first passive switching mixer and the second passive switching mixer and arranged to combine the first and the second down-converted signals such that harmonically down-converted signal content present in the first down-converted signal and harmonically down-converted signal content present in the second down-converted signal cancel in a combined output signal of the down-conversion circuit. The passive output combiner network is tunable to adjust magnitudes and phases of the first and the second down-converted signals. A related quadrature down-conversion circuit, a related receiver circuit, a related communication device, and a related calibration method are also disclosed.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

Disclosed herein is a broadcast signal receiver. The broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation module configured to perform detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to FEC-decode the PLP data, and an output processing module configured to receive the data of the at least one PLP and to output the received data in a data stream form.

A method for tuning an analog self-interference canceller includes detecting a tuning trigger, calculating a set of tuning parameters (the tuning parameters including complex weights for a set of taps of the analog self-interference canceller) in response to the tuning trigger, and applying the set of tuning parameters based on component calibration data.

A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.