These various embodiments serve to facilitate interlaced amplitude pulsing using a hard-tube type pulse generator having at least one energy-storage unit each comprising at least one energy-storing capacitor. Generally speaking, this comprises controlling an amount of energy withdrawn from the energy-storage unit and provided to an output load to form productive electric pulses by controlling at least one of: (1) energy replenishment; and (2) non-productive energy withdrawal of the energy-storage unit, to thereby achieve a series of productive interlaced amplitude electric pulses.

A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.

This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

The present invention is directed to communication systems. More specifically, embodiments of the present invention provide a technique and system thereof for performing eye modulation. Eye modulation is performed at the transmission side of a PAM communication system to compensate for distortion and non-linearity and generate an output waveform. Spacing among eye levels is adjusted by performing symmetric modulation using parameter and asymmetric modulation using parameter. A correction module measures the output waveform and sends feedback signals to a control module to adjust the parameter and the parameter. There are other embodiments as well.

A ternary pulse width modulation (PWM) method and apparatus. In one embodiment, the start of the pulse sequence in the current frame is referenced to the end of the pulse sequence in a previous, reference frame, rather than to the frame boundary at the start of the current frame, thereby allowing the compensation portion of the pulse sequence to overlap into the preceding or following frame, thus achieving a higher modulation index without dropping the compensation pulses. Although in most instantiations, the reference frame will be the frame immediately preceding in time the current frame, in other instances, the reference frame may be any frame preceding the current frame that falls within the constraints of the timing facility.