A ternary pulse width modulation (PWM) method and apparatus. In one embodiment, the start of the pulse sequence in the current frame is referenced to the end of the pulse sequence in a previous, reference frame, rather than to the frame boundary at the start of the current frame, thereby allowing the compensation portion of the pulse sequence to overlap into the preceding or following frame, thus achieving a higher modulation index without dropping the compensation pulses. Although in most instantiations, the reference frame will be the frame immediately preceding in time the current frame, in other instances, the reference frame may be any frame preceding the current frame that falls within the constraints of the timing facility.

The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.

A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of which jointly controlling the control inputs of a different pair; and a common output connecting between all N common points of all pairs of serially connected resistors forming the N voltage dividers.

A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of which jointly controlling the control inputs of a different pair; and a common output connecting between all N common points of all pairs of serially connected resistors forming the N voltage dividers.

The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

The present invention is directed to communication systems. More specifically, embodiments of the present invention provide a technique and system thereof for performing eye modulation. Eye modulation is performed at the transmission side of a PAM communication system to compensate for distortion and non-linearity and generate an output waveform. Spacing among eye levels is adjusted by performing symmetric modulation using parameter and asymmetric modulation using parameter. A correction module measures the output waveform and sends feedback signals to a control module to adjust the parameter and the parameter. There are other embodiments as well.

The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.