The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.

A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

Provided are a 3 level pulse amplitude modulation (PAM3) transmitter, an operating method of the PAM3 transmitter, and an electronic device including the same. The PAM3 transmitter includes a driver configured to convert input data into PAM3 signals, an eye monitor circuit electrically connected to an output terminal of the driver and configured to monitor upper eye patterns and lower eye patterns of the PAM3 signals, and a duty cycle adjust circuit configured to adjust a duty cycle of the input data provided to the driver.

Provided are a 3 level pulse amplitude modulation (PAM3) transmitter, an operating method of the PAM3 transmitter, and an electronic device including the same. The PAM3 transmitter includes a driver configured to convert input data into PAM3 signals, an eye monitor circuit electrically connected to an output terminal of the driver and configured to monitor upper eye patterns and lower eye patterns of the PAM3 signals, and a duty cycle adjust circuit configured to adjust a duty cycle of the input data provided to the driver.

The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.

The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

A low power PAM-4 output transmitter is disclosed. The lower power PAM-4 output transmitter comprises a first source series terminated SST branch configured to include unit cells having transistors which are selectively activated in response to an input signal outputted from an encoder; a second SST branch configured to include unit cells having transistors which are selectively activated in response to a negative signal of the input signal; and a common voltage switch H3 configured to short or open the first SST branch and the second SST branch. Here, differential signals are outputted from both terminals of the first SST branch and the second SST branch by making the first SST branch and the second SST branch short or open according to an operation of the common voltage switch.