A PFM control circuit includes a switching circuit, a slope-decision circuit, a flip-flop, a first and a second comparison circuits. The first comparison circuit outputs a first signal according to an output voltage of a power conversion circuit. The switching circuit outputs a switching signal according to an output current of the power conversion circuit. The slope-decision circuit outputs a slope modulation voltage, and determines a slope modulation voltage with a first or a second slope according to the switching signal. The second comparison circuit outputs the second signal according to the slope modulation voltage. The flip-flop outputs a control signal to the power conversion circuit according to the first and the second signals. When the slope modulation voltage has the first or the second slope, the control signal has a first or a second frequency accordingly. The first frequency is higher than the second frequency.

Wireless digital communication method for the communication between two electronic devices (3, 16) of an industrial apparatus (1), including—encoding each bit of information by a respective sequence of a certain number (N) of pulses (25) that alternate with a corresponding number (N−1) of silence intervals (26), each pulse having a pulse duration (TI) shorter than or equal to ns and said silence intervals having respective silence durations (TSj) longer than or equal to 30 ns—transmitting, by a first electronic device, a radio signal (RS) comprising a plurality of radio pulses corresponding to the sequence of pulses without modulating any radio carrier, and—receiving and decoding, by the other electronic device, said radio signal to obtain said bit of information. The method may include additional steps for exchanging information between the electronic devices according to which one of the electronic devices, while in a stand-by state, transmits a request message, waits for a reply message from the other electronic device (if and when some conditions are complied with) and, upon receiving the reply message, switches to an operating state in which the two electronic devices are communicatively coupled to each other.

A PFM control circuit includes a switching circuit, a slope-decision circuit, a flip-flop, a first and a second comparison circuits. The first comparison circuit outputs a first signal according to an output voltage of a power conversion circuit. The switching circuit outputs a switching signal according to an output current of the power conversion circuit. The slope-decision circuit outputs a slope modulation voltage, and determines a slope modulation voltage with a first or a second slope according to the switching signal. The second comparison circuit outputs the second signal according to the slope modulation voltage. The flip-flop outputs a control signal to the power conversion circuit according to the first and the second signals. When the slope modulation voltage has the first or the second slope, the control signal has a first or a second frequency accordingly. The first frequency is higher than the second frequency.

A method for generating an output signal having predetermined jitter characteristics is disclosed. A first signal is generated via a first signal generator module. A second signal is generated via a second signal generator module. The first signal is pulse position modulated by the second signal, thereby generating a modulated signal having predetermined jitter characteristics. An output signal having predetermined jitter characteristics is generated based on the modulated signal. Moreover, a signal generator for generating an output signal having predetermined jitter characteristics is disclosed.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

A method for generating an output signal having predetermined jitter characteristics is disclosed. A first signal is generated via a first signal generator module. A second signal is generated via a second signal generator module. The first signal is pulse position modulated by the second signal, thereby generating a modulated signal having predetermined jitter characteristics. An output signal having predetermined jitter characteristics is generated based on the modulated signal. Moreover, a signal generator for generating an output signal having predetermined jitter characteristics is disclosed.

Digital signal processing for mud pulse telemetry utilizes a variety of On/Off keying based modulation schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM), to encode and/or decode information. A combination of PPM and PWM is disclosed that increases a bit rate while keeping a chip rate unchanged. The combination of PPM and PWM comprises determining a drilling condition and forming a message based on the drilling condition, forming a string of symbol values comprising the message, identifying a pulse width and a pulse start for the pulse based on a symbol value, providing a first pulse at a selected chip location, providing subsequent pulses to form the pulse width, and forming a quiet period at the end of the pulse width.

A control device for a power semiconductor switch, includes an actuating device, a first current path, a second current path, which connects the second output of the actuating device to a circuit node of the control device in an electrically conductive manner, wherein the second current path incorporates an electrical switching off resistor which is electrically connected in-circuit between a second output of the actuating device and the circuit node of the control device, a third current path, which connects the circuit node of the control device to a control device terminal of the control device in an electrically conductive manner, and an switching off acceleration circuit, which is electrically connected in parallel with the switching off resistor, comprising a diode, an electrical resistor, and a capacitor which is electrically connected in parallel with said resistor, wherein the cathode of the diode is connected to a second electrical terminal of the capacitor in an electrically conductive manner, and a first electrical terminal of the capacitor is connected to a first terminal of the switching off resistor, which is electrically oriented towards the actuating device in an electrically conductive manner, and the anode of the diode is connected to a second electrical terminal of the switching off resistor in an electrically conductive manner.

A pulse position modulation circuit includes a delay locked loop circuit configured to include a plurality of delay circuits coupled in a cascade, each of the plurality of delay circuits being configured to delay an input signal by a time width corresponding to a control signal so as to generate an output signal, a plurality of pulse generation circuits, each of which is configured to generate a pulse with a pulse width corresponding to a phase difference between a first signal and a second signal which have different phases from each other at different timings corresponding to states of the first signal and the second signal, each of the first signal and the second signal being the input signal or the output signal of the plurality of delay circuits, and a selection circuit configured to select pulses generated by the plurality of pulse generation circuits.