Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Disclosed is a voltage converter capable of adaptively operating in one of a synchronous mode and an asynchronous mode according to an input voltage of an input terminal. The voltage converter includes: a voltage detector generating a detection result according to the input voltage; a switch control circuit generating a first switch control signal and a second switch control signal according to the detection result and an output voltage of an output terminal; a first switch intermittently turned on according to the first switch control signal in the synchronous and asynchronous modes; a second switch intermittently turned on/off according to the second switch control signal in the synchronous/asynchronous mode; and an energy storage circuit electrically connected to the input and output terminals to store and release energy according to the on-off states of the first and second switches.

Disclosed is a voltage converter capable of adaptively operating in one of a synchronous mode and an asynchronous mode according to an input voltage of an input terminal. The voltage converter includes: a voltage detector generating a detection result according to the input voltage; a switch control circuit generating a first switch control signal and a second switch control signal according to the detection result and an output voltage of an output terminal; a first switch intermittently turned on according to the first switch control signal in the synchronous and asynchronous modes; a second switch intermittently turned on/off according to the second switch control signal in the synchronous/asynchronous mode; and an energy storage circuit electrically connected to the input and output terminals to store and release energy according to the on-off states of the first and second switches.

Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

A switching power supply controller includes a pulse width modulator circuit. The pulse width modulator circuit includes a delay circuit and a delay control circuit coupled to the delay circuit. The delay control circuit includes an amplifier circuit. The amplifier circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first voltage reference terminal. The second input terminal is coupled to the second voltage reference terminal. The output terminal is coupled to a control terminal of the delay circuit.

A switching power supply controller includes a pulse width modulator circuit. The pulse width modulator circuit includes a delay circuit and a delay control circuit coupled to the delay circuit. The delay control circuit includes an amplifier circuit. The amplifier circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first voltage reference terminal. The second input terminal is coupled to the second voltage reference terminal. The output terminal is coupled to a control terminal of the delay circuit.

A pulse modulation circuit with a high-frequency-limiting function, including a comparator, an RS trigger, a switching triode, a NAND gate, a NOR gate, and a charging capacitor. A capacitor charging time is controlled by adjusting a bias current IB1, a bias current IB2, a reference voltage V1, and a reference voltage V2 or adjusting values of capacitors C1 and C2. In this way, a highest output frequency of a pulse generator is limited, so as to reduce hardware system overheads.