A power supply controller used in a DC/DC converter includes a feedback control unit that generates a pulse-shaped PWM signal having a first level that is one of a high level and a low level and a second level that is the other of the high level and the low level, on the basis of a feedback voltage based on an output voltage of the DC/DC converter; a low voltage detection unit that detects a low voltage of the feedback voltage; and a selection unit that chooses, as a chosen clock signal, a first clock signal having a high duty when the low voltage is not detected by the low voltage detection unit, and chooses a second clock signal having a low duty when the low voltage is detected by the low voltage detection unit. The feedback control unit includes a reset signal generation unit that generates a pulse-shaped reset signal having the first level and the second level, based on the feedback voltage, and a PWM signal generation unit that generates the PWM signal at the first level during a period that is an overlap between a period during which the reset signal is at the first level and a period during which the chosen clock signal is at the first level.

A power supply controller used in a DC/DC converter includes a feedback control unit that generates a pulse-shaped PWM signal having a first level that is one of a high level and a low level and a second level that is the other of the high level and the low level, on the basis of a feedback voltage based on an output voltage of the DC/DC converter; a low voltage detection unit that detects a low voltage of the feedback voltage; and a selection unit that chooses, as a chosen clock signal, a first clock signal having a high duty when the low voltage is not detected by the low voltage detection unit, and chooses a second clock signal having a low duty when the low voltage is detected by the low voltage detection unit. The feedback control unit includes a reset signal generation unit that generates a pulse-shaped reset signal having the first level and the second level, based on the feedback voltage, and a PWM signal generation unit that generates the PWM signal at the first level during a period that is an overlap between a period during which the reset signal is at the first level and a period during which the chosen clock signal is at the first level.

A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.

A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

The present specification provides a display apparatus allowing brightness of a display panel to be more finely controlled as compared with the related art. The display apparatus according to the present specification includes a display panel in which a plurality of pixels are arranged in m×n, and K shift register units configured to sequentially output pulse signals having a width adjusted to adjust brightness of the display panel to m horizontal pixel lines, wherein each of the shift register units includes m main flip-flops and m−1 sub-flip-flops connected between the in main flip-flops.

The present specification provides a display apparatus allowing brightness of a display panel to be more finely controlled as compared with the related art. The display apparatus according to the present specification includes a display panel in which a plurality of pixels are arranged in m×n, and K shift register units configured to sequentially output pulse signals having a width adjusted to adjust brightness of the display panel to m horizontal pixel lines, wherein each of the shift register units includes m main flip-flops and m−1 sub-flip-flops connected between the in main flip-flops.

Systems, methods, apparatuses for fan type identification are disclosed. A predetermined pulse width modulation duty cycle is used to obtain a sequence of fan speeds from a fan over a time period. A fan type of the fan is determined based on the sequence of fan speeds.

Systems, methods, apparatuses for fan type identification are disclosed. A predetermined pulse width modulation duty cycle is used to obtain a sequence of fan speeds from a fan over a time period. A fan type of the fan is determined based on the sequence of fan speeds.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.