A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

A filter circuit comprises a resistor-capacitor (RC) circuit, a comparator circuit, and an output control circuit. The RC circuit is configured to generate a ripple voltage according to the PWM signal. The comparator circuit couples with the RC circuit, and is configured to compare the ripple voltage with a first reference voltage, and output a switch signal according to a comparison result. The output control circuit couples with the comparator circuit and the RC circuit, and is configured to generate an output signal according to the switch signal and the PWM signal. When a duty ratio of the PWM signal is larger than a predetermined threshold value, the output signal is corresponding to the PWM signal. When the duty ratio of the PWM signal is smaller than the predetermined threshold value, the output signal is not corresponding to the PWM signal.

A filter circuit comprises a resistor-capacitor (RC) circuit, a comparator circuit, and an output control circuit. The RC circuit is configured to generate a ripple voltage according to the PWM signal. The comparator circuit couples with the RC circuit, and is configured to compare the ripple voltage with a first reference voltage, and output a switch signal according to a comparison result. The output control circuit couples with the comparator circuit and the RC circuit, and is configured to generate an output signal according to the switch signal and the PWM signal. When a duty ratio of the PWM signal is larger than a predetermined threshold value, the output signal is corresponding to the PWM signal. When the duty ratio of the PWM signal is smaller than the predetermined threshold value, the output signal is not corresponding to the PWM signal.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

Digital signal processing for mud pulse telemetry utilizes a variety of On/Off keying based modulation schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM), to encode and/or decode information. A combination of PPM and PWM is disclosed that increases a bit rate while keeping a chip rate unchanged. The combination of PPM and PWM comprises determining a drilling condition and forming a message based on the drilling condition, forming a string of symbol values comprising the message, identifying a pulse width and a pulse start for the pulse based on a symbol value, providing a first pulse at a selected chip location, providing subsequent pulses to form the pulse width, and forming a quiet period at the end of the pulse width.

A symbol rate determination method for determining a symbol rate of an input signal is disclosed. The method comprises: receiving the input signal; determining respective pulse widths of pulses contained in the input signal; allocating the pulse widths to groups based on a magnitude of the respective pulse widths; determining a group pulse width for each of the groups, the group pulse width being representative of the pulse widths contained in the respective group; and determining the symbol rate based on the determined group pulse widths. Moreover, a measurement instrument for determining a symbol rate of an input signal is disclosed.

A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.