A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.

A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.

A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

The present disclosure illustrates a demodulation circuit disposed in a wireless charging device. The demodulation circuit comprises a detection unit, a delay unit, a demodulation unit, a switch unit, an amplifier, an ADC, a control unit and a digital demodulation unit. The detection unit detects a pulse width modulation signal received by a coil, and outputs a modulation signal. The delay unit delays the modulation signal to generate a delay signal. The demodulation unit compares the modulation signal with the delay signal to generate a first demodulation signal. When the control unit detects the first demodulation signal is lower than a demodulation success rate in a time period, the control unit outputs a first switch signal to the switch unit. When the control unit detects a second demodulation signal is lower than the demodulation success rate in the time period, the control unit outputs a second switch signal to the switch unit.

The present disclosure illustrates a demodulation circuit disposed in a wireless charging device. The demodulation circuit comprises a detection unit, a delay unit, a demodulation unit, a switch unit, an amplifier, an ADC, a control unit and a digital demodulation unit. The detection unit detects a pulse width modulation signal received by a coil, and outputs a modulation signal. The delay unit delays the modulation signal to generate a delay signal. The demodulation unit compares the modulation signal with the delay signal to generate a first demodulation signal. When the control unit detects the first demodulation signal is lower than a demodulation success rate in a time period, the control unit outputs a first switch signal to the switch unit. When the control unit detects a second demodulation signal is lower than the demodulation success rate in the time period, the control unit outputs a second switch signal to the switch unit.

A data carrier apparatus includes a duty detector configured to determine a duty ratio of each pulse of a pulse signal that is received, a frequency detector configured to determine a period of each pulse of the pulse signal, and a demodulator configured to determine a value of data being carried by the pulse signal based on a determination result of the duty detector unit and a determination result of the frequency detector.

A data carrier apparatus includes a duty detector configured to determine a duty ratio of each pulse of a pulse signal that is received, a frequency detector configured to determine a period of each pulse of the pulse signal, and a demodulator configured to determine a value of data being carried by the pulse signal based on a determination result of the duty detector unit and a determination result of the frequency detector.

A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.

A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.