An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

Circuits and methods that provide wider bandwidth and smaller IM inductances for phase change material (PCM) based RF switch networks. The present invention recognizes that it is beneficial to consider the total high parasitic capacitance to ground of the various PCM switches in an RF switch network as constituting two or more separate capacitive contributions. This leads to several “split capacitance” concepts, including signal-path splitting, switch-block splitting, stacked-switch splitting, and splitting parasitic capacitances due to layout discontinuities, in which compensating impedance matching inductances are inserted between additive capacitances.

An electronic device is provided. The electronic device includes a tunable component and a first source follower circuit. The tunable component is electrically connected to a circuit node. The first source follower circuit is electrically connected to the circuit node. The first source follower circuit includes a first control terminal and a first terminal. The first control terminal is electrically connected to the first terminal.

A control system for independent alternating-input (“IAI”) devices includes multiple IAI devices and an analog switch component. The control system may also include a bus-generating component. The analog switch component includes multiple switches configured to connect of disconnect input connection points of the analog switch component and voltage input points of the IAI devices. The analog switch component opens or closes switches, responsive to a digital control signal, to provide voltage signals to the voltage input points of the IAI devices. In some cases, the IAI devices activate or deactivate based on the provided voltage signals. In some cases, the bus-generating component provides a first voltage signal to a first voltage input point of an IAI device, and the analog switch component controls the switches to provide a second voltage signal to a second voltage input point of the IAI device.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

A circuit architecture and process that provides for a dual-mode methodology for an RF integrated circuit (IC) switch circuit that allows switching between a direct mapping configuration and a fully decoded mapping configuration, and further provides for changing either mapping configuration after fabrication. A control word is selectively compared to a programmed map register value so that, in a first mode, only one bit position of a control word matches a decoded programmed map bit pattern, and in a second mode, all bits of a control word match a corresponding programmed map bit pattern. Because the map registers can be programmed at least once after IC fabrication, the exact mapping required for a particular application can be determined post fabrication. Further, the first mode of operation is often beneficial during testing because multiple RF signal paths can be turned on at the same time and thus tested in parallel.

An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

In a switching circuit, an inductance of an inductor of a shunt circuit is such that off capacitance of a second switching device that is in the off state when a first switching device is in the on state is used to define, in the shunt circuit, a series resonance circuit with a desired resonant frequency. Therefore, the frequency of an unnecessary signal to be attenuated is set to the resonant frequency of the series resonance circuit. Thus, the switching circuit achieves improved isolation characteristics with other circuits by attenuating the unnecessary signal.

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).