A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.

A switch circuit provided on a substrate includes a first series switch and a second series switch disposed in series on a path connecting a first terminal and a second terminal, a third series switch and a fourth series switch disposed in series on a path connecting the first terminal and a third terminal, a first shunt switch connected to a common ground terminal and a first node between the first series switch and the second series switch, and a second shunt switch connected to the common ground terminal and a second node between the third series switch and the fourth series switch.

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.

An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.

A capacitive sensing device includes an antenna electrode for emitting an alternating electric field in response to an alternating voltage caused in the antenna electrode and a control and evaluation circuit that includes a transimpedance amplifier configured to maintain the alternating voltage equal to an alternating reference voltage on a reference voltage node by injecting a current into the antenna electrode and to measure the current. The control and evaluation circuit includes a microcontroller and a multiplexer configured and arranged to switch the antenna electrode alternately to a current input of the transimpedance amplifier and to the alternating reference voltage node. The microcontroller is configured to control the multiplexer. The multiplexer and the transimpedance amplifier and a low-pass filter operatively connected to the transimpedance amplifier form together a synchronous rectifier arrangement. The current input node of the transimpedance amplifier is AC-coupled to the reference voltage node by a protection capacitor.

According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.

Examples of a system and method are disclosed herein. An example of the system includes a first computer having a port and a first operating system to execute on the first computer. The system also includes a second computer coupled to the port of the first computer to receive power from the first computer, the second computer having a second operating system to simultaneously execute on the second computer. The system additionally includes a circuit to selectively switch between a first context supported by the first operating system of the first computer and a second context supported by the second operating system without waiting to save the first and second contexts.

An element array circuit includes one or more first wirings, second wirings, impedance elements, one or more operational amplifiers, one or more first selectors, and one or more second selectors. The one or more first selectors each select one option from a first option group including a first option to apply a first potential to one of respective one or more first ends of the one or more first wirings and a second option to apply a second potential different from the first potential to the one of the one or more first ends. The one or more second selectors each select one option from a second option group including a third option to apply the first potential to one of respective one or more second ends of the first wiring(s) and a fourth option to apply the second potential to the one of the one or more second ends.

A switch assembly includes a PIN diode connected between an antenna port and a receive port, a first shunt FET device connected between the receive port and ground, a first series FET device connected between the antenna port and a transmit port, a second shunt FET device connected between the transmit port and ground, and a plurality of bias control contacts configured to receive a corresponding plurality of bias control voltages to forward bias the first shunt FET device and the first series FET device into an ON state and to reverse bias the PIN diode and the second shunt FET device into an OFF state in a transmit mode, and to reverse bias the first shunt FET device and the first series FET device into the OFF state and to forward bias the PIN diode and the second shunt FET device into the ON state in a receive mode.