A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch includes switching transistors coupled in series, referred to as stacked transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. The charge injection control elements include resistors or transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as stacked transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

Embodiments described herein include a solid-state switch tube replacement for the radar system such as, for example, the SPY-1 radar system. Some embodiments provide for a technology for the precision switching that enables IGBT power modules to operate robustly in a series configuration and/or a parallel configuration to produce precision switching at high voltage (e.g., 20 kV and above) and high frequencies (e.g., 1 MHz and above).

A semiconductor device of an embodiment includes semiconductor layer including first and second planes, and in order from the first plane's side to the second plane's side, first region of first conductivity type, second region of second conductivity type, third region of second conductivity type having second conductivity type impurity concentration higher than the second region, fourth region of first conductivity type, and fifth region of second conductivity type, and including first and second trench on the first plane's side; first gate electrode in the first trench; first gate insulating film in contact with the fifth semiconductor region; second gate electrode in the second trench; second gate insulating film; a first electrode on the first plane; second electrode on the second plane; first gate electrode pad connected to the first gate electrode; and second gate electrode pad connected to the second gate electrode.

Apparatus and methods for biasing radio frequency (RF) switches to achieve fast switching are disclosed herein. In certain configurations, a switch bias circuit generates a switch control voltage for turning on or off a switch that handles RF signals. The switch bias circuit provides the switch control voltage to a control input of the switch by way of a resistor. Additionally, the switch bias circuit pulses the switch control voltage when turning on or off the switch to thereby shorten switching time. Thus, the switch can be turned on or off quickly, which allows the switch to be available for use soon after the state of the switch has been changed.

In a PIN diode drive circuit, a forward voltage is applied to a PIN diode through a first switching element and a reverse voltage is applied to the PIN diode through a second switching element. A limiting unit limits an increase rate of an absolute value of a reverse recovery current to a value smaller than a threshold value, the reverse recovery current flowing through the PIN diode when a voltage applied to the PIN diode changes from a forward voltage to a reverse voltage. The threshold value is less than 1 time and 0.5 times or more of a maximum value of the increase rate when a second peak appears regarding the reverse recovery current.

A gate driving apparatus for a power semiconductor device may include: a first off-resistor and a second off-resistor each having a first end connected to a gate of the power semiconductor device; a first off-switch configured to determine a connection state between a second end of the first off-resistor and a ground based on a gate driving signal for determining an on/off state of the power semiconductor device; a second off-switch configured to determine a connection state between a second end of the second off-resistor and the ground; an electric current detector configured to detect an electric current flowing from a collector (drain) of the power semiconductor device to an emitter (source) of the power semiconductor device; and a controller configured to determine an open/closed state of the second off-switch based on the gate driving signal and a magnitude of the electric current detected by the electric current detector.