A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

A voltage supply circuit includes a level shifter that switches between voltages of two voltage input units and that outputs one of the voltages, a charge pump that transforms a voltage of an input power supply and that applies the transformed voltage to the level shifter, and a charge pump control circuit. The voltage supply circuit controls supply and interruption of a predetermined voltage to a voltage-supplied circuit (RF switch 20). The charge pump control circuit causes the charge pump to perform a continuous operation in an on-mode and to perform an intermittent operation in an off-mode, the off-mode representing a state in which the voltage supply to the voltage-supplied circuit (RF switch 20) is stopped, the on-mode representing a state in which the predetermined voltage is supplied.

A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

A gate driving apparatus for a power semiconductor device may include: a first off-resistor and a second off-resistor each having a first end connected to a gate of the power semiconductor device; a first off-switch configured to determine a connection state between a second end of the first off-resistor and a ground based on a gate driving signal for determining an on/off state of the power semiconductor device; a second off-switch configured to determine a connection state between a second end of the second off-resistor and the ground; an electric current detector configured to detect an electric current flowing from a collector (drain) of the power semiconductor device to an emitter (source) of the power semiconductor device; and a controller configured to determine an open/closed state of the second off-switch based on the gate driving signal and a magnitude of the electric current detected by the electric current detector.

The drive circuit for driving voltage controlled switches includes: charge path connected to gate of the switch, through which gate charge current flows to turn the switch ON; discharge path connected to the gate and output terminal of the switch, through which gate discharge current flows to turn the switch OFF; and at least either, a charging side element disposed on charging side loop path having the gate, a part of the charge path and the output terminal, restricting current flow to be in one direction and not disturbing current flow of charge current; or a discharging side element disposed on a discharging side loop path having the gate, a part of the discharge path and the output terminal, restricting a current flow to be in one direction and not disturbing a current flow of discharge current.

A system comprises a buffer circuit coupled to a comparator, and an adaptive threshold control circuit coupled to a timer and comparator. Buffer circuit receives a first voltage across a control terminal and a first current terminal of a transistor and a second voltage across a second current terminal and the first current terminal of the transistor. Comparator compares first voltage to a first threshold, generating a first trigger signal when it crosses first threshold, and compares second voltage to a second threshold, generating a second trigger signal when it crosses second threshold. Timer determines length of time between trigger signals. Adaptive threshold control circuit generates a first control signal for first trigger signal, and a second control signal for second trigger signal, and provides a control signal to comparator indicative of whether length of time is greater than or less than user-programmed value, causing comparator to adjust first threshold.

A system comprises a buffer circuit coupled to a comparator, and an adaptive threshold control circuit coupled to a timer and comparator. Buffer circuit receives a first voltage across a control terminal and a first current terminal of a transistor and a second voltage across a second current terminal and the first current terminal of the transistor. Comparator compares first voltage to a first threshold, generating a first trigger signal when it crosses first threshold, and compares second voltage to a second threshold, generating a second trigger signal when it crosses second threshold. Timer determines length of time between trigger signals. Adaptive threshold control circuit generates a first control signal for first trigger signal, and a second control signal for second trigger signal, and provides a control signal to comparator indicative of whether length of time is greater than or less than user-programmed value, causing comparator to adjust first threshold.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.