A power source supply circuit includes: a plurality of power sources (11-1, 11-2) that generate power source voltages different from each other; a switch circuit (14) that switches and outputs the power source voltages generated in the plurality of power sources (11-1, 11-2); a voltage output terminal (16) that outputs outside the power source voltages output from the switch circuit (14); an RF choke circuit (15) provided between the switch circuit (14) and the voltage output terminal (16), the RF choke circuit (15) including a first capacitor; and a second capacitor (12-1, 12-2) provided between the plurality of power sources (11-1, 11-2) and the switch circuit (14), the second capacitor (12-1, 12-2) having a larger capacitance than the first capacitor.

An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.

An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.

Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.

Driver unit for a voltage-controlled switching element, includes a first output terminal for connecting a control terminal of the switching element, a second output terminal for connecting a further terminal of the switching element, an output stage section having a high-side terminal and a low-side terminal and being controllable to connect one of its terminals to the first output terminal of the driver unit based on a control signal representative switching the switching element, and a DC conversion section configured to supply the output stage section and to convert an input voltage into a positive first voltage between the high-side terminal and the second output terminal of the driver unit and into a positive second voltage between the second output terminal of the driver unit and the low-side terminal.

The present invention provides a drive device and a power supply system capable of driving a power transistor with low power while reflecting variations in manufacture process and external environments. A trigger detection circuit monitors a voltage between terminals or a current between terminals in a switching period of a power transistor and detects that the voltage between terminals or the current between terminals reaches a predetermined reference value. A current switching circuit selects a register outputting a current value to a variable current driver circuit from a plurality of registers and switches the register to be selected using a detection result of the trigger detection circuit as a trigger in the switching period, thereby making the drive current of the variable current driver circuit shift.

A drive device wherein a main switching element is connected to a main current path, an input terminal of the switching element on the higher potential side and an output terminal of the switching element on the lower potential side are electrically connected to a control terminal of the main switching element, a first resistance is connected between an input terminal of the switching element on the lower potential side and a control terminal of the main switching element, a first capacitor is parallelly connected to the first resistance, and a second capacitor is connected between a connection point of the first resistance and a control terminal of the main switching element and a terminal on the higher potential side of the main switching element.

Devices, methods and techniques related to ultrafast latching switches are disclosed. In one example aspect, a device includes a photoconductive switch and a non-mechanical latching switch configured to maintain a state after the state is activated. The non-mechanical latching switch is coupled to the photoconductive switch. The non-mechanical latching switch is configured to be triggered to switch to an opposite state upon an activation of the photoconductive switch.

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.