A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

In one aspect, a solid-state switching apparatus is provided that includes a pair of anti-parallel thyristors, a quasi-resonant turn-off circuit, a sensor, and a control circuit. The turn-off circuit is coupled in parallel with the pair of anti-parallel thyristors and includes a first selectively conductive path and a second selectively conductive path. The sensor is configured to sense a thyristor current conducted by at least one of the pair of anti-parallel thyristors. The control circuit is configured to receive the sensed thyristor current from the sensor and determine a magnitude of the sensed thyristor current and a polarity of the sensed thyristor current. The control circuit is further configured to activate, in response to determining that the magnitude is greater than a threshold value, one of the first selectively conductive path and the second selectively conductive path based on the polarity to commutate and interrupt the thyristor current.

An RF switch circuit is provided. The RF switch circuit may include a first switch disposed between a transmitting port and an antenna port and including a plurality of first transistors; a second switch disposed between the antenna port and a receiving port and including a plurality of second transistors; and a switch control circuit configured to generate control voltages to control the first transistors and the second transistors, generate a first Off voltage to turn off at least one first transistor among the plurality of first transistors and the plurality of second transistors in a transmitting mode, and generate a second Off voltage to turn off at least one second transistor among the plurality of first transistors and the plurality of second transistors in a receiving mode, wherein the second Off voltage may be higher than the first Off voltage.

An RF switch circuit is provided. The RF switch circuit may include a first switch disposed between a transmitting port and an antenna port and including a plurality of first transistors; a second switch disposed between the antenna port and a receiving port and including a plurality of second transistors; and a switch control circuit configured to generate control voltages to control the first transistors and the second transistors, generate a first Off voltage to turn off at least one first transistor among the plurality of first transistors and the plurality of second transistors in a transmitting mode, and generate a second Off voltage to turn off at least one second transistor among the plurality of first transistors and the plurality of second transistors in a receiving mode, wherein the second Off voltage may be higher than the first Off voltage.