A surgical retractor assembly for providing surgical exposure. The surgical retractor assembly consists of multiple ring segments connected by adjustable ratchet mechanisms to form a complete ring. The ratchet mechanisms are attached to tissue retractor blades which provide exposure of the wound when expanded, without the requirement of a direct connection/attachment to an operating table. The tissue retractor blades are attached in a manner which is adjustable and facilitates the ability of the overall surgical retractor assembly (ring segments and connectors) to be raised or lowered with respect to the patient. The ring segments also allow attachments of additional retractor blades or other surgical retractor accessories for additional surgical exposure.

A load drive circuit includes a power source terminal (“PST”), a power source and a load terminal connecting a load to the power source. A semiconductor switch connects the PST to the load terminal. A control circuit includes an output terminal for opening/closing the semiconductor switch. A freewheeling circuit includes a freewheeling diode and a protection switch blocks a current from the power source to the semiconductor switch when the power source is connected in a reverse manner. A first terminal connects the control circuit to a first fixed potential and a second terminal connects an anode of the freewheeling diode to a second fixed potential. A connection circuit includes a connection switch connecting the output terminal and the first terminal. The connection circuit connects the output terminal to the first terminal when a rise in a potential difference between the first terminal and the second terminal is detected.

A semiconductor unit includes a semiconductor device, a controller, and a resistor. The semiconductor device includes a transistor arranged between a positive electrode of a battery and an inverter circuit electrically connected to the battery. The controller is connected to a control terminal of the transistor and configured to control the transistor. The resistor arranged between the control terminal and the controller. The controller controls the transistor so that when a current flowing to the transistor is greater than or equal to a threshold value, the transistor is deactivated. The resistor has a resistance value that is greater than or equal to 100Ω.

A semiconductor unit includes a semiconductor device, a controller, and a resistor. The semiconductor device includes a transistor arranged between a positive electrode of a battery and an inverter circuit electrically connected to the battery. The controller is connected to a control terminal of the transistor and configured to control the transistor. The resistor arranged between the control terminal and the controller. The controller controls the transistor so that when a current flowing to the transistor is greater than or equal to a threshold value, the transistor is deactivated. The resistor has a resistance value that is greater than or equal to 100Ω.

Circuit assembly for protecting a unit to be operated from a supply network against surges, comprising an input having a first and a second input connection, which are connected to the supply network, an output to which the unit to be protected can be connected, and a protective circuit which is placed between the first and the second input connections in order to limit the voltage applied thereto, said protective circuit comprising a power semiconductor device. The power semiconductor device includes at least one Zener element between the collector and the gate, or a digital-to-analog converter is placed between the collector and the gate of the power semiconductor device. The protective level of this type of protective circuit can be easily adjusted by setting the clamping voltage for the power semiconductor device.

A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.

The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

A drive circuit includes: a control section generating a control signal; a first level shift section raising a level of a signal from the control section; a high side drive section controlling a semiconductor device; and a second level shift section lowering a level of a signal from the high side drive section for input to the control section. The high side drive section has an error detection section maintaining an output of an error detection signal when the semiconductor device is in an error status until a release signal is input, the control section has an error handling section outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section, and the error detection section stops the output of the error detection signal when the release signal is input.