This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

An active gate driver suitable for activating an electronic switch of an electric motor. The active gate driver includes a pull up branch, a pull down branch and a current and voltage feedback from an output of the active gate driver to at least one input of the active gate driver, wherein the current and voltage feedback is common to both the pull up branch and the pull down branch.

A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

The present description concerns a method of controlling a bidirectional switch (200), including: first (210 1) and (210 2) field-effect transistors electrically in series between first (262 1) and second (262 2) terminals of the bidirectional switch; third (614) and fourth (612) field-effect transistors electrically in series between said first and second terminals of the bidirectional switch, a first connection node (252) in series with the first and second transistors being common with a second connection node (616) in series with the third and fourth transistors, including steps of: receiving a voltage (V200) between the terminals of the bidirectional switch; detecting, from the received voltage, a first sign of said voltage; at least while the first sign is being detected, coupling the first terminal to said first node (252), potentials of control terminals of the first, second, third, and fourth transistors being referenced to the potential (REF) of the first and second nodes having common sources of the first, second, third, and fourth transistors connected thereto.

A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.