A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.

A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage.

A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.

A semiconductor switching circuit, for use in a HVDC power converter, comprising: a main semiconductor switching element, including first and second connection terminals between which current flows from the first connection terminal to the second connection terminal and an auxiliary semiconductor switching element electrically connected between the first and second connection terminals thereof, and a control unit, operatively connected to auxiliary semiconductor switching element and programmed to control the switching element to create an alternative current path between the first and second connection terminals by at least two of: a fully-on mode in which the switching element is operated at its maximum rated base current or gate voltage; a pulsed switched mode in which the switching element is turned on and off; and an active mode in which the switching element is operated with a continuously variable base current or gate voltage.

An electronic device includes at least one electronic component, a gradient heat-flux sensor GHFS based on thermoelectric anisotropy and conducting heat generated by the electronic component, and a controller adapted to manage electrical current of the electronic component at least partly on the basis of an electrical control signal generated by the gradient heat-flux sensor and proportional to a heat-flux through the gradient heat-flux sensor. Therefore, the electrical current and thereby also the heat generation of the electronic component are managed directly on the basis of the heat-flux generated by the electronic component. Thus, the electrical current can be managed without a need for voltage and current measurements which may be challenging to be carried out with a sufficient bandwidth especially when the switching frequency of the electronic component is on a range from hundreds of kHz to few MHz.