Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with a first auxiliary path and the main path in series with a second auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the first auxiliary path. The circuit assembly also includes a third gate bias network connected to the second auxiliary path, the second gate bias network and the third gate bias network configured to improve linearity of the switching function.

Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.

A driving circuit that drives an insulated-gate semiconductor device. The driving circuit includes a constant-current generation circuit and a discharge circuit. The constant-current generation circuit has first and second transistors forming a current mirror, and a constant-current circuit connected to the drain of the first transistor for providing a constant current to the current mirror. The discharge circuit is connected to a gate of the insulated-gate semiconductor device and the drain of the second transistor, and includes a third transistor. The discharge circuit is configured to draw out a current injected into the gate of the insulated-gate semiconductor device by inputting a driving signal to the gate of the third transistor, and correct a metal-oxide-semiconductor (MOS) size of the third transistor so as to adjust an amount of a current that flows via the drain and the source of the third transistor to ground.

An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.

A gate drive device for driving a plurality of semiconductor devices connected in parallel to each other includes a constant current circuit, a plurality of switching element, and a drive controller. The constant current circuit supplies a constant current to respective gates of the plurality of semiconductor devices. The plurality of switching elements is respectively provided on a plurality of paths that connects the constant current circuit and the respective gates of the plurality of semiconductor devices. The drive controller controls driving of the plurality of switching elements to supply the constant current from the constant current circuit to the respective gates of the plurality of semiconductor devices.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

In one embodiment, a circuit includes a plurality of elementary transistors connected in parallel between a node of application of a first potential of a power supply voltage and a node for coupling a load. The plurality of transistors includes a first assembly of elementary transistors having their gates coupled to a control node by a first circuit and a second assembly of elementary transistors having their gates coupled to the control node by a second circuit. The second circuit has two states, where the first and second circuits are configured to supply a substantially identical control voltage to the gates of the first and second assemblies of elementary transistors when the second circuit is in one of the two states.

A driver circuit includes two high-side switches and a single low-side switch, output inductor, and output capacitor. By having multiple high-side switches, the driver can regulate power from multiple charging devices. The high-side switches share a channel with an input capacitor for that channel and the channels are connected to the low-side switch at a common node. When the capacitor for one of the channels becomes charged quickly, the capacitor of the other channel will balance itself with the charged capacitor. To avoid damaging the high-side switches, a low-impedance bridge and driver circuit is connected between the channels.