An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

Methods and apparatus for a body diode conduction sensor configured for coupling to a switching element. In embodiments, the sensor comprises first and second voltage divider networks coupled to a voltage source and a diode coupled to the switching element and to the first voltage divider network, wherein the diode is conductive at times corresponding to body diode conduction of the switching element decreasing the DC average voltage at the output node of the first voltage divider network. A differential output voltage can be coupled to the first and second voltage divider networks with an output signal corresponding to a time of the body diode conduction of the switching element.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

A voltage selection circuit, including: first and second nodes of application of first and second input voltages; a third output voltage supply node; first and second MOS transistors respectively coupling the first and third nodes and the second and third nodes; and a control circuit capable of keeping the first and second transistors either respectively on and off or respectively off and on, the control circuit including a feedback loop from the third node to the gate of the first transistor and being capable, during a transition phase, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node.

A voltage selection circuit, including: first and second nodes of application of first and second input voltages; a third output voltage supply node; first and second MOS transistors respectively coupling the first and third nodes and the second and third nodes; and a control circuit capable of keeping the first and second transistors either respectively on and off or respectively off and on, the control circuit including a feedback loop from the third node to the gate of the first transistor and being capable, during a transition phase, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node.

An electric power converter includes an electric gatedriver circuit that includes a transformer. The transformer includes separate first and second cores of magnetically conductive material that are shaped to form respective closed loops. The transformer also includes a first electrical conductor with at least one winding arranged around a part of the first core in a first winding direction and at least one winding arranged around a part of the second core in a second winding direction opposite the first winding direction. The transformer further includes a second electrical conductor with at least one winding arranged around a part of the first core in the first winding direction and at least one winding arranged around a part of the second core in the second winding direction so as to counteract electric influence induced by a common magnetic field through the closed loops of the first and second cores.

In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.

A primary transmitter drives a primary-side input of an isolation barrier in response to a transition of an input signal. A secondary receiver generates an output signal having a logical value that corresponds to a signal that occurs at a secondary-side output of the isolation barrier. A secondary transmitter drives a secondary-side input of the isolation barrier based on the output signal. A primary receiver generates a return signal having a logical value that corresponds to a signal that occurs at a primary-side output of the isolation barrier. The primary transmitter repeatedly drives the primary-side input of the isolation barrier until the logical value of the input signal matches that of the return signal.