A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize a switch of the inverter with a pulse width modulation (PWM) signal. The gate driver is configured to delay the PWM signal by a dependent amount that is a function of a magnitude of current of a lead of the electric machine. The delay is responsive to a polarity of the current being positive.

A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize a switch of the inverter with a pulse width modulation (PWM) signal. The gate driver is configured to delay the PWM signal by a dependent amount that is a function of a magnitude of current of a lead of the electric machine. The delay is responsive to a polarity of the current being positive.

A passive timing circuit for optocoupled relay has a rail having an output for an input terminal of the optocoupled relay. The circuit also has a capacitive network between the rail and ground. The capacitance of the capacitive network can be configured according to a timing period and the circuit does not require a voltage source other than that applied by the input terminal which, over the time period, increases voltage of the rail until the relay switches.

A passive timing circuit for optocoupled relay has a rail having an output for an input terminal of the optocoupled relay. The circuit also has a capacitive network between the rail and ground. The capacitance of the capacitive network can be configured according to a timing period and the circuit does not require a voltage source other than that applied by the input terminal which, over the time period, increases voltage of the rail until the relay switches.

An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.