The invention provides a converter and a method for suppressing loop interference of converter. The converter includes first and second switching sets connected to each other. Each switching set includes a plurality of switching devices. The plurality of second switching devices are configured to be turned on for a first time after the turn-off time of the plurality of first switching devices, such that each of the plurality of second switching devices provides a path for current within the first time to reduce a potential difference between the first end of at least one of the plurality of second switching devices and the first end of the remaining of the plurality of second switching devices.

The invention provides a converter and a method for suppressing loop interference of converter. The converter includes first and second switching sets connected to each other. Each switching set includes a plurality of switching devices. The plurality of second switching devices are configured to be turned on for a first time after the turn-off time of the plurality of first switching devices, such that each of the plurality of second switching devices provides a path for current within the first time to reduce a potential difference between the first end of at least one of the plurality of second switching devices and the first end of the remaining of the plurality of second switching devices.

A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

Provided is a technique for reducing the size and cost of a semiconductor device. A semiconductor device includes an IGBT module having an IGBT, and a MOSFET module having a MOSFET whose operational property is different from that of the IGBT, the MOSFET module being connected to the IGBT module in parallel. The semiconductor device is capable of selectively executing an operation mode in which switching timing in the IGBT module and switching timing in the MOSFET module are non-identical.

Provided is a technique for reducing the size and cost of a semiconductor device. A semiconductor device includes an IGBT module having an IGBT, and a MOSFET module having a MOSFET whose operational property is different from that of the IGBT, the MOSFET module being connected to the IGBT module in parallel. The semiconductor device is capable of selectively executing an operation mode in which switching timing in the IGBT module and switching timing in the MOSFET module are non-identical.

A switching device for conducting and disconnecting electric currents includes: a first mechanical contact assembly; a semiconductor switch, which is in parallel to the first mechanical contact assembly; a second mechanical contact assembly, which is connected in series to the first mechanical contact assembly; and a switching electronics, which switch on and off the semiconductor switch. The switching electronics are operable, during a closing process of the first mechanical contact assembly, to turn on the semiconductor switch after a first predetermined time period t0 after initialization of the switching electronics, and to turn the semiconductor switch off again after a second predetermined time period t1. The first predetermined time period t0 is set by the switching electronics depending on the first mechanical contact assembly.

A switching device for conducting and disconnecting electric currents includes: a first mechanical contact assembly; a semiconductor switch, which is in parallel to the first mechanical contact assembly; a second mechanical contact assembly, which is connected in series to the first mechanical contact assembly; and a switching electronics, which switch on and off the semiconductor switch. The switching electronics are operable, during a closing process of the first mechanical contact assembly, to turn on the semiconductor switch after a first predetermined time period t0 after initialization of the switching electronics, and to turn the semiconductor switch off again after a second predetermined time period t1. The first predetermined time period t0 is set by the switching electronics depending on the first mechanical contact assembly.

Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.

Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.