A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Provided is a driving apparatus that includes a gate driving circuit that turns off a first semiconductor element upon receiving a turn-off signal, a measuring circuit that measures a parameter according to a voltage applied to the second semiconductor element, a timing generating circuit that generates a timing signal if the parameter satisfies a first condition during a time period in which the first semiconductor element is tuned off; and a driving condition change circuit that, in response to the timing signal, further decreases a changing speed of a gate voltage of the first semiconductor element than a reference speed during the time period in which the first semiconductor element is tuned off, wherein the gate driving circuit turns off the first semiconductor element in response to that the parameter satisfies a second condition during a time period in which the first semiconductor element is tuned on.

A drive circuit of a voltage-controlled power semiconductor element, including first to fourth switching elements, first and second delay circuits, an overcurrent detection circuit, a slow shutdown detection circuit and a flip-flop. The first switching element turns on upon receiving an off signal. The second switching element is turned on by the first delayed signal generated by the first delay circuit. The third switching element turns on upon receiving a second delayed signal generated by the second delay circuit through the flip-flop. The fourth switching element is turned on by the slow shutdown detection signal generated by the slow shutdown detection circuit. The first to fourth switching elements extract electric charges from the gate terminal of the voltage-controlled power semiconductor element, with first to fourth extracting capabilities, respectively. The first and fourth extracting capabilities are larger than the third extracting capability and smaller than the second extracting capability.

A low-voltage protective device includes: at least one outer conductor path from an outer conductor power terminal of the low-voltage protective device to an outer conductor load terminal of the low-voltage protective device; a neutral conductor path from a neutral conductor terminal of the low-voltage protective device to a neutral conductor load terminal of the low-voltage protective device; a mechanical bypass switch arranged in the outer conductor path; a first semiconductor circuit arrangement connected in parallel to the mechanical bypass switch, the first semiconductor circuit arrangement having at least one power semiconductor, such as an IGBT, with a control terminal, such as a gate terminal; an electronic control unit; a current-measurement arrangement arranged in the outer conductor path, connected to the electronic control unit of the protective device; and at least one voltage measurement arrangement for detecting a Miller effect-induced voltage spike at the at least one power semiconductor.

Provided is a transmission device for transmitting and receiving data through a transmission channel. The transmission device includes a transmission circuit unit configured to transmit data to the transmission channel. When an overcurrent caused by a simultaneous transmission of data to the transmission channel is detected during data transmission, the transmission circuit unit increases an output resistance, which is a resistance value for an output to the transmission channel, to an resistance value corresponding to a characteristic of a facility equipment item that transmits data to the transmission channel at the same time as itself.

A hybrid drive circuit (100, 100′) drives a first characteristic transistor and a second characteristic transistor coupled in parallel to the first characteristic transistor according to an input signal (Sin). The hybrid drive circuit (100, 100′) includes a first turn-on path (Pc1), a first turn-off path (Ps1), a second turn-on path (Pc2), and a second turn-off path (Ps2). The first turn-on path (Pc1) and the second turn-on path (Pc2) produce a first delay time to delay turning on the first characteristic transistor. The first turn-off path (Ps1) and the second turn-off path (Ps2) produce a second delay time to delay turning off the second characteristic transistor.

A system to regulate power from a first power supply to a load coupled to the first power supply, wherein a power transistor is coupled between the load and ground. The system includes: a transistor having a control terminal, a first current terminal adapted to be coupled to an external second power supply and a second current terminal adapted to be coupled to a control terminal of the power transistor; a first resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to a first terminal of a second external capacitor, the first node of the first resistor is adapted to be coupled to a first terminal of a first external capacitor; a second resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to ground, the first node of the second resistor is adapted to be coupled to a first terminal of an first external resistor; and wherein a second terminal of the first external capacitor is coupled to a node between the load and a first current terminal of the power transistor and a second terminal of the second external capacitor is coupled to form a capacitive divider with the first external capacitor and the first resistor, and a second node of the first external resistor is coupled to the node between the load and the first current terminal of the power transistor to form a resistive divider with the second resistor.

A system to regulate power from a first power supply to a load coupled to the first power supply, wherein a power transistor is coupled between the load and ground. The system includes: a transistor having a control terminal, a first current terminal adapted to be coupled to an external second power supply and a second current terminal adapted to be coupled to a control terminal of the power transistor; a first resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to a first terminal of a second external capacitor, the first node of the first resistor is adapted to be coupled to a first terminal of a first external capacitor; a second resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to ground, the first node of the second resistor is adapted to be coupled to a first terminal of an first external resistor; and wherein a second terminal of the first external capacitor is coupled to a node between the load and a first current terminal of the power transistor and a second terminal of the second external capacitor is coupled to form a capacitive divider with the first external capacitor and the first resistor, and a second node of the first external resistor is coupled to the node between the load and the first current terminal of the power transistor to form a resistive divider with the second resistor.