A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer.

A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer.

A system includes an electric motor, at least one pair of high side and low side switches connected to the electric motor, and a microcontroller connected to the high side and low side switches. At least the low side switches have a minimum on-time requirement. The microcontroller controls the switches by outputting a pulse-width modulation (PWM) signal. At least the PWM signal outputted to the low side switch is center-aligned to the off-time. When a request is made to the microcontroller resulting in a low side on-time of zero with a previous duty cycle request that is greater than a predetermined threshold, the microcontroller is constructed and arranged to extend the duty cycle of the low side switch of the at least one pair of switches into the next period to a duration of the required minimum on-time.

A description is given below of an intelligent semiconductor switch and also a method for operating an intelligent semiconductor switch integrated in a chip package. In accordance with one exemplary embodiment, the method comprises, in a first mode, in which a state control signal having a first logic level is received at a control terminal of the chip package, driving a first and a second semiconductor switch of a half-bridge in accordance with an input signal received at an input terminal of the chip package. In a second mode, in which a state control signal having a second logic level is received at the control terminal of the chip package, the method comprises setting an operating parameter depending on a pulse pastern of the input signal received at the input terminal.

A description is given below of an intelligent semiconductor switch and also a method for operating an intelligent semiconductor switch integrated in a chip package. In accordance with one exemplary embodiment, the method comprises, in a first mode, in which a state control signal having a first logic level is received at a control terminal of the chip package, driving a first and a second semiconductor switch of a half-bridge in accordance with an input signal received at an input terminal of the chip package. In a second mode, in which a state control signal having a second logic level is received at the control terminal of the chip package, the method comprises setting an operating parameter depending on a pulse pastern of the input signal received at the input terminal.

An electric assembly includes an insulated gate bipolar transistor device, a wide-bandgap transistor device electrically connected in parallel with the bipolar transistor device and a control circuit. The control circuit is electrically coupled to a gate terminal of the bipolar transistor device and to a control terminal of the wide-bandgap transistor device. The control circuit is configured to turn on the bipolar transistor device and to turn on the wide-bandgap transistor device at a predefined turn-on delay with respect to a turn-on of the bipolar transistor device.

An electric assembly includes an insulated gate bipolar transistor device, a wide-bandgap transistor device electrically connected in parallel with the bipolar transistor device and a control circuit. The control circuit is electrically coupled to a gate terminal of the bipolar transistor device and to a control terminal of the wide-bandgap transistor device. The control circuit is configured to turn on the bipolar transistor device and to turn on the wide-bandgap transistor device at a predefined turn-on delay with respect to a turn-on of the bipolar transistor device.

A hybrid drive circuit (100, 100) drives a first characteristic transistor and a second characteristic transistor coupled in parallel to the first characteristic transistor according to an input signal (Sin). The hybrid drive circuit (100, 100) includes a first turn-on path (Pc1), a first turn-off path (Ps1), a second turn-on path (Pc2), and a second turn-off path (Ps2). The first turn-on path (Pc1) and the second turn-on path (Pc2) produce a first delay time to delay turning on the first characteristic transistor. The first turn-off path (Ps1) and the second turn-off path (Ps2) produce a second delay time to delay turning off the second characteristic transistor.