Provided is a driving apparatus that includes a gate driving circuit that turns off a first semiconductor element upon receiving a turn-off signal, a measuring circuit that measures a parameter according to a voltage applied to the second semiconductor element, a timing generating circuit that generates a timing signal if the parameter satisfies a first condition during a time period in which the first semiconductor element is tuned off; and a driving condition change circuit that, in response to the timing signal, further decreases a changing speed of a gate voltage of the first semiconductor element than a reference speed during the time period in which the first semiconductor element is tuned off, wherein the gate driving circuit turns off the first semiconductor element in response to that the parameter satisfies a second condition during a time period in which the first semiconductor element is tuned on.

A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.

A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.

A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.

A system to regulate power from a first power supply to a load coupled to the first power supply, wherein a power transistor is coupled between the load and ground. The system includes: a transistor having a control terminal, a first current terminal adapted to be coupled to an external second power supply and a second current terminal adapted to be coupled to a control terminal of the power transistor; a first resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to a first terminal of a second external capacitor, the first node of the first resistor is adapted to be coupled to a first terminal of a first external capacitor; a second resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to ground, the first node of the second resistor is adapted to be coupled to a first terminal of an first external resistor; and wherein a second terminal of the first external capacitor is coupled to a node between the load and a first current terminal of the power transistor and a second terminal of the second external capacitor is coupled to form a capacitive divider with the first external capacitor and the first resistor, and a second node of the first external resistor is coupled to the node between the load and the first current terminal of the power transistor to form a resistive divider with the second resistor.

A system to regulate power from a first power supply to a load coupled to the first power supply, wherein a power transistor is coupled between the load and ground. The system includes: a transistor having a control terminal, a first current terminal adapted to be coupled to an external second power supply and a second current terminal adapted to be coupled to a control terminal of the power transistor; a first resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to a first terminal of a second external capacitor, the first node of the first resistor is adapted to be coupled to a first terminal of a first external capacitor; a second resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to ground, the first node of the second resistor is adapted to be coupled to a first terminal of an first external resistor; and wherein a second terminal of the first external capacitor is coupled to a node between the load and a first current terminal of the power transistor and a second terminal of the second external capacitor is coupled to form a capacitive divider with the first external capacitor and the first resistor, and a second node of the first external resistor is coupled to the node between the load and the first current terminal of the power transistor to form a resistive divider with the second resistor.

There is provided a power supply control apparatus for connection to electrical inputs of an electronic device wherein each electrical input is operatively connected to a power source having a sequencer circuit and a control element, the sequencer circuit including sequencer stage(s). The sequencer circuit selectively receives an indication signal, the sequencer circuit selectively receives a positive indication signal indicative of a voltage supplied to a first of the electrical inputs reaching or passing a predefined voltage threshold, and the sequencer circuit selectively provides a control signal to the control element, the control element triggerable by a positive control signal. Each sequencer stage includes circuit elements, the first selectively receives an input signal and selectively provides an intermediate signal to the second, the second selectively provides an output signal.

There is provided a power supply control apparatus for connection to electrical inputs of an electronic device wherein each electrical input is operatively connected to a power source having a sequencer circuit and a control element, the sequencer circuit including sequencer stage(s). The sequencer circuit selectively receives an indication signal, the sequencer circuit selectively receives a positive indication signal indicative of a voltage supplied to a first of the electrical inputs reaching or passing a predefined voltage threshold, and the sequencer circuit selectively provides a control signal to the control element, the control element triggerable by a positive control signal. Each sequencer stage includes circuit elements, the first selectively receives an input signal and selectively provides an intermediate signal to the second, the second selectively provides an output signal.