A power distribution circuit can include a comparator circuit that is formed of an inverter. The inverter can be configured with a trip voltage value (Vtrip) different than half a supply voltage value (VDD/2) for further energy efficiencies in discharging a charge storage device used in the power distribution circuit to gain security.

A communication system includes a supply generator configured to generate a modulated supply according to a data transmission; a light emitting diode (LED) emulator including an emulator input coupled to the supply generator and an emulator output configured to output a sense voltage, wherein the emulator input is configured to receive a forward current derived from the modulated supply and translate the forward current into the sense voltage; a voltage comparator coupled to the emulator output and configured to receive the sense voltage and translate the sense voltage into a modulated output signal based on a communication voltage threshold; and a transmitter coupled to a comparator output and configured to receive the modulated output signal and generate a communication signal according to the data transmission based on the modulated output signal.

A transistor circuit having a dummy capacitor or a dummy transistor between an input terminal and a transistor is disclosed. The circuit improves secondary nonlinear characteristics of the transistor attributable to one or more parasitic components and a clock signal. The transistor circuit includes an input terminal configured to receive an input signal, a transistor having a gate configured to receive a clock signal, and a source connected to the input terminal, a connection line between the input terminal and the transistor and having a parasitic resistor therein, a parasitic capacitor between the input terminal and the transistor, and a dummy transistor having a first terminal that is connected to the connection line between the input terminal and the transistor.

Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.

An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.

According to one embodiment, in electronic apparatus, controller generates first and second control signals to control first and second controlled unit. First serial converter multiplexes the first and second control signals into first serial signal. First wireless transmitter transmits the first serial signal by first wireless signal in a chronologically continuous manner. First wireless receiver receives the first wireless signal. First parallel converter separates the first and second control signals from the first wireless signal received by first wireless receiver, to output the first control signal to first controlled unit, and to output the second control signal to second controlled unit.

According to one embodiment, in electronic apparatus, controller generates first and second control signals to control first and second controlled unit. First serial converter multiplexes the first and second control signals into first serial signal. First wireless transmitter transmits the first serial signal by first wireless signal in a chronologically continuous manner. First wireless receiver receives the first wireless signal. First parallel converter separates the first and second control signals from the first wireless signal received by first wireless receiver, to output the first control signal to first controlled unit, and to output the second control signal to second controlled unit.

A power module includes a switching element, a temperature detection part which detects an operation temperature T of the switching element, a control electrode voltage control part which controls a control electrode voltage based on a threshold voltage Vth during an operation of the switching element which is calculated based on information including the operation temperature T of the switching element detected by the temperature detection part, and a switching speed control part which controls a switching speed of the switching element based on the operation temperature T of the switching element detected by the temperature detection part.