In certain embodiments, driver circuitry generates drive signals to drive driven circuitry to transition between first and second states. The driver circuitry has a first-to-second driver circuit that generates a first drive signal to drive the driven circuitry to transition from the first state to the second state and a second-to-first driver circuit that generates a second drive signal to drive the driven circuitry to transition from the second state to the first state. The driver circuitry includes two complementary triggered current pulse generators (described in U.S. Pat. No. 10,554,206) that combine to efficiently provide switch drive for a FET or other reactive load. The triggered drive has fast edges for low switching losses. In certain embodiments, the low power triggered drive circuitry can respond to a slowly changing feedback signal to switch a FET so as to regulate a power converter output.

Differential sampling circuits may be adversely affected by changes in common mode voltage. Changes in the common mode voltage may alter the on resistance of transistor switches which it turn may mean that small signal changes are not correctly observed against a bigger common mode signal. The present disclosure relates to a way of improving the ability to resolve small differential signal changes by varying the supply or drive voltage to a component to compensate for common mode voltage changes.

Example implementations relate to dual rail circuitry using FET pairs. For example, a circuit according to the present disclosure may include a first field-effect transistor (FET) pair coupled to a dual rail circuitry, a second FET pair coupled to the dual rail circuitry, and a controller coupled to the first FET pair and the second FET pair. The controller may switch a power supply to the dual rail circuitry using the first FET pair and the second FET pair. The dual rail circuitry may provide a power supply to a computing device from a first power supply coupled to the first FET pair or a second power supply coupled to the second FET pair.

A power gating circuit includes a first switch circuit, a gate circuit, and a second switch circuit. The first switch circuit is configured to disconnect a first voltage line from a second voltage line while a logic block connected to the first voltage line is in a first operation state. The gate circuit is configured to output a control signal having a first logical value if a level of a first voltage on the first voltage line is lower than a reference level while the logic block is in the first operation state. The second switch circuit configured to connect the first voltage line to the second voltage line based on the first logical value of the control signal. The reference level is based on a type of a logic gate included in the gate circuit.

A switching device includes: a lower switching element, an upper switching element having a source connected to a drain of the lower switching element; a control circuit including a first output part that supplies a driving signal to the lower switching element; a Zener diode having a cathode connected to the first output part; a parallel capacitor connected to the Zener diode in parallel; a resistor connected between an anode of the Zener diode and a gate of the lower switching element; and a gate-side capacitor provided separate from a parasitic capacitance of the lower switching element, having a larger capacitance than the parasitic capacitance of the lower switching element, and connected, outside the lower switching element, between the gate and a source of the lower switching element. The capacitance of the gate-side capacitor is smaller than a capacitance of the parallel capacitor.

A controller for a system includes a first control section and a second control section. The system includes an electrical actuator, a switch switching the electrical actuator between a power supply state and a power cutoff state, and a drive section driving the switch. The drive section outputs, to the switch, a drive signal to drive the switch based on a command signal for switching of the switch. The first control section determines a switch state based on the command signal, and the second control section determines a switch state based on the drive signal. At least one of the first control section and the second control section determines the electrical actuator to be in the power supply state on the condition that the first control section determines the switch to be in the power supply state, and the second control section also determines the switch to be in the power supply state.

A controller for a system includes a first control section and a second control section. The system includes an electrical actuator, a switch switching the electrical actuator between a power supply state and a power cutoff state, and a drive section driving the switch. The drive section outputs, to the switch, a drive signal to drive the switch based on a command signal for switching of the switch. The first control section determines a switch state based on the command signal, and the second control section determines a switch state based on the drive signal. At least one of the first control section and the second control section determines the electrical actuator to be in the power supply state on the condition that the first control section determines the switch to be in the power supply state, and the second control section also determines the switch to be in the power supply state.

A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.

A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.

A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.