A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.

A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.

A switching circuit includes a first input/output terminal, a second input/output terminal, a third input/output terminal, a first transistor, a second transistor, an inductor and a resistor. The first transistor is electrically connected between the first input/output terminal and the second input/output terminal. The second transistor is electrically connected between the first input/output terminal and the third input/output terminal. The inductor and the resistor are electrically connected in series with each other between the second input/output terminal and the third input/output terminal.

In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

Turn-on and turn-off of a semiconductor device are controlled through control of a gate voltage in accordance with a driving control signal. At a first time after a start of a Miller period of a gate voltage in driving a gate of the semiconductor device in accordance with the driving control signal, a driving signal is changed from 1 to 0 to thereby make a gate driving ability temporarily lower than the gate driving ability during a period from a starting time of the turn-on operation to the first time. Further, at a second time corresponding to an end of the Miller period, the driving signal is changed from 0 to 1 to thereby increase the gate driving ability.

A method for identifying correct operation of an electrical switching unit, having a full bridge circuit and inductive load operated by the full bridge circuit. The full bridge circuit includes a first semiconductor switching element supplying the inductive load with a first supply voltage potential and a second semiconductor switching element supplying the inductive load with a second supply voltage potential, having a smaller value than the first supply voltage potential. The first and second semiconductor switching element each have a diode. The method determines that the first semiconductor switching element changes from an activated state into a deactivated state, measures a voltage applied to the second semiconductor switching element, compares the measured voltage with a first threshold and detecting that, if the measured voltage on the second semiconductor switching element falls below the second supply voltage potential by the predefined first threshold, the electrical switching unit is operating correctly.

A method for identifying correct operation of an electrical switching unit, having a full bridge circuit and inductive load operated by the full bridge circuit. The full bridge circuit includes a first semiconductor switching element supplying the inductive load with a first supply voltage potential and a second semiconductor switching element supplying the inductive load with a second supply voltage potential, having a smaller value than the first supply voltage potential. The first and second semiconductor switching element each have a diode. The method determines that the first semiconductor switching element changes from an activated state into a deactivated state, measures a voltage applied to the second semiconductor switching element, compares the measured voltage with a first threshold and detecting that, if the measured voltage on the second semiconductor switching element falls below the second supply voltage potential by the predefined first threshold, the electrical switching unit is operating correctly.

The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.

A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.