A circuit comprises an optical coupling including an illuminator optically coupled to an optical sensor to output a voltage from the optical sensor based on intensity of illumination from the illuminator. The circuit includes a voltage input node with a resistance connected in series between the voltage input and a Zener diode. A method includes powering an illuminator with current from a first voltage input node. The method includes sensing illumination level in illumination from the illuminator with a sensor and outputting output proportionate to illumination sensed by the sensor indicative of voltage detected at the voltage input node. The method can include limiting current between the voltage input node and the illuminator.

A power converter provides a low-voltage output using a full-bridge fault-tolerant rectification circuit. The output circuit uses controlled switches as rectifiers. A fault detection circuit monitors circuit conditions. Upon detection of a fault, the switches are disabled decoupling the power converter from the system. A common-source dual MOSFET device includes a plurality of elements arranged in alternating patterns on a semiconductor die. A common-source dual synchronous rectifier includes control circuitry powered from the drain to source voltage of the complementary switch. A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. A clamp phase may be used to reduce power losses in the converter at light loads, control the effective output resistance of the converter, effectively regulate the voltage transformation ratio, provide narrow band output regulation, and control the rate of change of output voltage for example during start up. One or more of the transformer windings may be clamped. The converter may use the sine amplitude converter topology. The converter may use common-source dual MOSFET devices and fault detection. The density of point of load power conversion may be increased and the associated power dissipation reduced by removing the input driver circuitry from the point of load where it is not necessary. An output circuit may be located at the point of load providing fault tolerant rectification of the AC power from the secondary winding of a power transformer which may be located nearby the output circuit. The resonant voltage and current waveforms on the primary side of the transformer are readily communicated via an AC bus between the driver circuit and the primary winding of the power transformer. The driver circuit may drive a plurality of transformer-output circuit pairs. The transformer and output circuit may be combined in a single module at the point of load. Alternatively, the output circuit may be integrated into point of load circuitry such as a processor core. The transformer may be deployed near the output circuit.

The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to a voltage of the first terminal, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the voltage of the first terminal. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

A switching power supply device includes: a latch circuit to be set by a latch signal that is generated when an anomaly is detected, the latch circuit stopping the turning ON and OFF of the switching element when set by the latch signal; a pulse generator that receives said latch signal and generates a pulse signal at a prescribed cycle in response to said latch signal; a discharge circuit that is activated every time said pulse signal is provided so as to discharge electric charges stored in the capacitor; and a comparator for undervoltage protection that, when said control power supply voltage decreases to a prescribed operation stop voltage as said capacitor discharges, resets the latch circuit and the pulse generator, respectively.

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

An alternator and a rectifier thereof are provided. The rectifier includes a transistor and a gate voltage control circuit. A control end of the transistor receives a gate voltage. The gate voltage control circuit generates the gate voltage according to a voltage difference between an input voltage and a rectified voltage. The gate voltage control circuit detects a first time point when the voltage difference is less than a first preset threshold voltage, provides the gate voltage during a first time interval after the first time point to turn on the transistor, and sets the voltage difference to a first reference voltage. The gate voltage control circuit regulates the gate voltage to set the voltage difference to a second reference voltage during a second time interval after the first time interval. The first time interval is independent of a cycle of the input voltage.

Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.

Circuits and methods allowing virtually any number of batteries to be connected in parallel without the supply voltage being substantially reduced, while allowing their capacities to add directly as well as increasing the current capability of the batteries by placing the batteries' internal resistances in parallel.