A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.

An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

A circuit comprises an optical coupling including an illuminator optically coupled to an optical sensor to output a voltage from the optical sensor based on intensity of illumination from the illuminator. The circuit includes a voltage input node with a resistance connected in series between the voltage input and a Zener diode. A method includes powering an illuminator with current from a first voltage input node. The method includes sensing illumination level in illumination from the illuminator with a sensor and outputting output proportionate to illumination sensed by the sensor indicative of voltage detected at the voltage input node. The method can include limiting current between the voltage input node and the illuminator.

According to one embodiment, a semiconductor device includes a semiconductor member, a gate electrode, a source electrode, a drain electrode, a conductive member, a gate terminal, and a first circuit. The semiconductor member includes a first semiconductor layer including a first partial region and including Al.sub.x1Ga.sub.1−x1N (0≤x1≤1), and a second semiconductor layer including Al.sub.x2Ga.sub.1−x2N (0<x2≤1 and x1<x2). The first partial region is between the gate electrode and at least a portion of the conductive member in a first direction. The gate terminal is electrically connected to the gate electrode. The first circuit is configured to apply a first voltage to the conductive member based on a gate voltage applied to the gate terminal. The first voltage has a reverse polarity of a polarity of the gate voltage.

During an ON period of a high breakdown voltage switch provided within an ON period of a semiconductor switching element, a detection circuit outputs to a predetermined node a voltage obtained by dividing an inter-terminal voltage by a plurality of resistor elements. A voltage comparison circuit outputs a detection signal indicating whether or not the inter-terminal voltage is greater than a predetermined determination voltage based on a comparison between the voltage of the predetermined node and a predetermined DC voltage. The high breakdown voltage switch has a breakdown voltage greater than a potential difference between a high potential and a low potential during an OFF period.

A switching device includes a first switch and a threshold voltage adjustment circuitry. The first switch is configured to be selectively turned on according to an enable signal, in order to connect a first pin to a second pin. The threshold voltage adjustment circuitry is configured to adjust a voltage level of a bulk terminal of the first switch according to the enable signal and a voltage provided from a power source. In response to the voltage being de-asserted, the threshold voltage adjustment circuitry is further configured to cut off a signal path between the bulk terminal and the power source.

Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes a first set of SCRC switches and a second set of SCRC switches electrically connected between power supply lines and power reception lines. The first set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and the second operational mode. The second set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and electrically isolate the power supply lines from the power reception lines in the second operational mode. Activation of the first set of SCRC switches is staggered in time with activation of the second set of SCRC switches. The second set of SCRC switches is spaced among the first set of SCRC switches.

Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes a first set of SCRC switches and a second set of SCRC switches electrically connected between power supply lines and power reception lines. The first set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and the second operational mode. The second set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and electrically isolate the power supply lines from the power reception lines in the second operational mode. Activation of the first set of SCRC switches is staggered in time with activation of the second set of SCRC switches. The second set of SCRC switches is spaced among the first set of SCRC switches.

The present disclosure relates to a field-effect transistor (FET) controlling apparatus and method for accurately, controlling an operation state of a FET by adaptively adjusting a voltage applied to the FET to correspond to a voltage of a source terminal of the FET. The voltage applied to the gate terminal of the FET may be adaptively controlled according to the voltage of the source terminal using a capacitor. Therefore, even when the source terminal is not connected to the ground but connected to an external load, there is an advantage that the operation state of the FET may be smoothly and accurately controlled. In addition, there is an advantage that a voltage within a certain range may be applied to the gate terminal of the FET.

The present disclosure relates to circuitry for driving a load. The circuitry comprises driver circuitry configured to generate a drive signal, based on an input signal to the driver circuitry, for driving the load, and commutator circuitry for coupling the driver circuitry to the load. The commutator circuitry is configured to alternate between commutation states in response to a level of the drive signal meeting a drive signal threshold or in response to a level of the input signal meeting a first input signal threshold. The circuitry is configured to apply an offset to the input signal when the input signal is below a second input signal threshold so as to increase a minimum level of the drive signal above the drive signal threshold or to increase a minimum level of the input signal above the first input signal threshold.